about holdtime，setuptime，clk skew，jitter（English，pdf，2 EDAyuan）

pamelamay

【文件名】:06413@52RD_有关时序setup，hold，skew，jitter.rar
【格　式】:rar
【大　小】:130K
【简　介】:When a logic block completes an operation, it will generate a completion signal DV to indicate that output data is valid. The handshaking signals then initiate a data transfer to the next block, which latches in the new data and begins a new computation by asserting the initialization signal I. Asynchronous designs are advantageous because computations are performed at the native speed of the logic, where block computations occur whenever data becomes available. There is no need to manage clock skew, and the design methodology leads to a very modular approach where interaction between blocks simply occur through a handshaking procedure. However, these handshaking protocols result in increased complexity and overhead in communication that can reduce performance.
【目　录】:无目录