串口接收程序有几点不明白，求助

tonywang000

以下是串口接收程序，有几点不明白：
1.
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
这段代码的作用是什么？为什么要定义这个？

2.next_bit是不是在wire next_bit = (bit_spacing==4'd10);这句之后就一直保持4'd10不变？

3.
always @(posedge clk)
        if(Baud8Tick)
        begin
                if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11)
                        RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
                else if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00)
                        RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
       
                if(RxD_cnt_inv==2'b00)
                        RxD_bit_inv <= 1'b0;
                else if(RxD_cnt_inv==2'b11)
                        RxD_bit_inv <= 1'b1;
        end
这部分语句的作用是什么？


以下是整个程序：
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006

module receive_test(clk, RxD,  RxD_data );

input clk, RxD;                // 系统时钟， 接收信号
output [7:0] RxD_data;        // 接收的数据，进入后级的 RAM 数据总线


parameter ClkFrequency = 50_000_000; // 25MHz
parameter Baud = 9600;

// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire [Baud8GeneratorAccWidth:0] Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];

////////////////////////////
reg [1:0] RxD_sync_inv;
always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
// we invert RxD, so that the idle becomes "0",
// to prevent a phantom character to be received at startup

reg [1:0] RxD_cnt_inv;
reg RxD_bit_inv;

always @(posedge clk)
        if(Baud8Tick)
        begin
                if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11)
                        RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
                else if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00)
                        RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
       
                if(RxD_cnt_inv==2'b00)
                        RxD_bit_inv <= 1'b0;
                else if(RxD_cnt_inv==2'b11)
                        RxD_bit_inv <= 1'b1;
        end

reg [3:0] state;
reg [3:0] bit_spacing;

// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);

always @(posedge clk)
if(state==0)
        bit_spacing <= 4'b0000;
else
if(Baud8Tick)
        bit_spacing <= {bit_spacing[2:0] + 4'b0001} | {bit_spacing[3], 3'b000};

always @(posedge clk)
if(Baud8Tick)
case(state)
        4'b0000:
                if(RxD_bit_inv)
                begin
                        state <= 4'b1000;  // start bit found?
                       
                end
       
        4'b1000: if(next_bit) state <= 4'b1001;  // bit 0
        4'b1001: if(next_bit) state <= 4'b1010;  // bit 1
        4'b1010: if(next_bit) state <= 4'b1011;  // bit 2
        4'b1011: if(next_bit) state <= 4'b1100;  // bit 3
        4'b1100: if(next_bit) state <= 4'b1101;  // bit 4
        4'b1101: if(next_bit) state <= 4'b1110;  // bit 5
        4'b1110: if(next_bit) state <= 4'b1111;  // bit 6
        4'b1111: if(next_bit) state <= 4'b0001;  // bit 7
       
        4'b0001:
                if(next_bit)
               
                        state <= 4'b0000;  // stop bit
                       
               
        default:
        begin
                state <= 4'b0000;
       
        end       
endcase

reg [7:0] RxD_data;
always @(posedge clk)
        if(Baud8Tick && next_bit && state[3])
                RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};





endmodule