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wcdma518

【文件名】:081228@52RD_OMAP3430_ES3.0_DM_Operating_Condition_Addendum_v1.0.pdf
【格　式】:pdf
【大　小】:456K
【简　介】:
【目　录】:


OMAP3430 Multimedia Processor Silicon Revision 3.0
Data Manual Operating Condition Addendum Version 1.0
June, 2008
PAGE: 1/11
TI Internal Data
Signed NDA Required
for Distribution

TABLE OF CONTENTS
1 INTRODUCTION.......................................................................................................................................6
2 RECOMMENDED OPERATION..............................................................................................................7
2.1 PROCESSOR CLOCKS.............................................................................................................................7
2.2 DEVICE CORE CLOCKS.........................................................................................................................10

wcdma518

【文件名】:081228@52RD_OMAP34xx_DM_Delta_ES2.0_ES2.1_vK_to_ES3.0_vA.pdf
【格　式】:pdf
【大　小】:1006K
【简　介】:
【目　录】:



OMAP34xx Multimedia Processor
Silicon Revision 3.0
(Texas Instruments OMAPTM Family of Products)
DATA MANUAL
Delta between ES2.0 ES2.1 vK and ES3.0 vA
May 2008

OMAP34xx ES3.0 DM Delta Introduction ....................................................................5
1 Chapter 1: Introduction ..............................................................................................6
2 Chapter 2: Terminal Description................................................................................7
2.1 ProDB00092521 & ProDB00095550 & ProDB00096231 & 34xx-080527-030: Terminal
Description Update ................................................................................................................................. 7
3 Chapter 3: Electrical Characteristics ......................................................................20
3.1 34xx-080514-026: Absolute Maximum Ratings Clarification ...................................................... 20
4 Chapter 4: Clock Specifications ..............................................................................21
4.1 34xx-080320-021: xtalin & xtalout Crystal Clock Accuracy Update............................................ 21
5 Chapter 5: Video DAC Specifications .....................................................................22
6 Chapter 6: Timing Requirements and Switching Characteristics ........................23
6.1 34xx-080520-028: Low Voltage OPP Mode Update For ES3.0.................................................. 23
6.2 34xx-080507-025: DSS and RFBI I/O Interfaces Timings Update For ES3.0 ............................ 24
6.3 34xx-080523-029: SDI Interface Flatlink3G Mode Timings Added............................................. 29
7 Chapter 7: Package Characteristics........................................................................32
7.1 34xx-080515-027: Device Nomenclature Description Update For ES3.0................................... 32
8 Chapter 8: Glossary ..................................................................................................33

wcdma518

【文件名】:081228@52RD_OMAP34xx_ES3.0_POP_DM_V_C.rar
【格　式】:rar
【大　小】:2101K
【简　介】:
【目　录】:




1 INTRODUCTION ................................................................................................................. 15
2 TERMINAL DESCRIPTION.................................................................................................... 16
2.1 Terminal Assignment ...................................................................................................... 16
2.2 Ball Characteristics......................................................................................................... 17
2.3 Multiplexing Characteristics ............................................................................................... 45
2.4 Signal Description .......................................................................................................... 53
2.4.1 External Memory Interfaces .................................................................................... 53
2.4.2 Video Interfaces ................................................................................................. 56
2.4.3 Serial Communication Interfaces .............................................................................. 59
2.4.4 Removable Media Interfaces................................................................................... 65
2.4.5 Test Interfaces ................................................................................................... 67
2.4.6 Miscellaneous .................................................................................................... 69
2.4.7 General-Purpose IOs ........................................................................................... 69
2.4.8 System and Miscellaneous Terminals ........................................................................ 73
2.4.9 Power Supplies .................................................................................................. 75
3 ELECTRICAL CHARACTERISTICS........................................................................................ 77
3.1 Power Domains............................................................................................................. 77
3.2 Absolute Maximum Ratings............................................................................................... 79
3.3 Recommended Operating Conditions ................................................................................... 82
3.4 DC Electrical Characteristics ............................................................................................. 83
3.5 Core Voltage Decoupling.................................................................................................. 86
3.6 Power-up and Power-down ............................................................................................... 88
3.6.1 Power-up Sequence ............................................................................................ 88
3.6.2 Power-down Sequence ......................................................................................... 90
4 CLOCK SPECIFICATIONS.................................................................................................... 91
4.1 Input Clock Specifications................................................................................................. 92
4.1.1 Clock Source Requirements ................................................................................... 92
4.1.2 External Crystal Description.................................................................................... 92
4.1.3 Clock Squarer Input Description............................................................................... 93
4.1.4 External 32-kHz CMOS Input Clock .......................................................................... 95
4.1.5 External sys_altclk CMOS Input Clock ....................................................................... 95
4.2 Output Clock Specifications............................................................................................... 96
4.3 DPLL and DLL Specifications ............................................................................................ 97
4.3.1 Digital Phase-Locked Loop (DPLL) ........................................................................... 98
4.3.1.1 DPLL1 (MPU) ......................................................................................... 98
4.3.1.2 DPLL2 (IVA2) ......................................................................................... 98
4.3.1.3 DPLL3 (CORE)........................................................................................ 99
4.3.1.4 DPLL4 (Peripherals).................................................................................. 99
4.3.1.5 DPLL5 (Second peripherals DPLL) ................................................................ 99
4.3.2 Delay-Locked Loops (DLL)..................................................................................... 99
4.3.3 DPLLs and DLL Characteristics ............................................................................... 99
4.3.4 DPLL and DLL Noise Isolation ............................................................................... 100
5 VIDEO DAC SPECIFICATIONS............................................................................................ 102
5.1 Interface Description ..................................................................................................... 102
5.2 Electrical Specifications Over Recommended Operating Conditions .............................................. 103
5.3 Analog Supply (vdda_dac) Noise Requirements ..................................................................... 104
5.4 External Component Value Choice..................................................................................... 106
6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ............................................ 107
6.1 Timing Test Conditions................................................................................................... 107
6.2 Interface Clock Specifications........................................................................................... 107
Contents 3
TI Internal Data — Signed NDA Required for Distribution
OMAP34xx Multimedia Device
Silicon Revision 3.0
SWPS034C–JUNE 2008–REVISED JULY 2008 www.ti.com
6.2.1 Interface Clock Terminology.................................................................................. 107
6.2.2 Interface Clock Frequency.................................................................................... 107
6.2.3 Clock Jitter Specifications..................................................................................... 107
6.2.4 Clock Duty Cycle Error ........................................................................................ 107
6.3 Timing Parameters ....................................................................................................... 108
6.4 External Memory Interfaces ............................................................................................. 108
6.4.1 General-Purpose Memory Controller (GPMC) ............................................................. 108
6.4.1.1 GPMC/NOR Flash Synchronous Timing ......................................................... 109
6.4.1.2 GPMC/NOR Flash Asynchronous Timing........................................................ 116
6.4.1.3 GPMC/NAND Flash Asynchronous Timing ..................................................... 124
6.4.2 SDRAM Controller Subsystem (SDRC)..................................................................... 129
6.4.2.1 SDRC/SDR SDRAM Interface Timing............................................................ 129
6.4.2.2 SDRC/DDR SDRAM Interface Timing............................................................ 132
6.5 Video Interfaces........................................................................................................... 146
6.5.1 Camera Interface .............................................................................................. 146
6.5.1.1 First Camera Serial Interface (CSI2) Timing .................................................... 146
6.5.1.2 Second Camera Serial Interface (CSIb) Timing................................................. 148
6.5.1.3 Parallel Camera Interface Timing ................................................................. 150
6.5.2 Display Subsystem (DSS) .................................................................................... 161
6.5.2.1 LCD Display in Bypass Mode ..................................................................... 161
6.5.2.2 LCD Display in RFBI Mode ........................................................................ 163
6.5.3 Display Serial Interface (DSI)................................................................................. 166
6.5.3.1 DSI in High-Speed Mode........................................................................... 166
6.5.3.2 DSI in Low-Power Mode and Ultralow-Power Mode ........................................... 167
6.5.4 Serial Display Interface (SDI)................................................................................. 168
6.5.4.1 SDI in Flatlink™ 3G Mode ......................................................................... 168
6.6 Serial Communications Interfaces...................................................................................... 171
6.6.1 Multichannel Buffered Serial Port (McBSP) Timing ....................................................... 171
6.6.1.1 McBSP in Normal Mode............................................................................ 171
6.6.1.2 McBSP in TDM – Multipoint Mode (McBSP3)................................................... 179
6.6.2 Multichannel Serial Port Interface (McSPI) Timing ........................................................ 180
6.6.2.1 McSPI in Slave Mode............................................................................... 180
6.6.2.2 McSPI in Master Mode ............................................................................. 181
6.6.3 Dual-Port Synchronous Serial Interface (SSI) Timing..................................................... 183
6.6.4 Multiport Full-Speed Universal Serial Bus (FS-USB) Interface .......................................... 184
6.6.4.1 Multiport Full-Speed Universal Serial Bus (FS-USB) – Unidirectional Standard 6-pin
Mode.................................................................................................. 184
6.6.4.2 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional Standard 4-pin
Mode.................................................................................................. 185
6.6.4.3 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional Standard 3-pin
Mode.................................................................................................. 186
6.6.4.4 Multiport Full-Speed Universal Serial Bus (FS-USB) – Unidirectional TLL 6-pin Mode ... 188
6.6.4.5 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional TLL 4-pin Mode ..... 189
6.6.4.6 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional TLL 3-pin Mode ..... 190
6.6.5 Multiport High-Speed Universal Serial Bus (HS-USB) Timing ........................................... 191
6.6.5.1 High-Speed Universal Serial Bus (HS-USB) on Port 0 – 12-bit Slave Mode................ 192
6.6.5.2 High-Speed Universal Serial Bus (HS-USB) on Ports 1 and 2 – 12-bit Master Mode ..... 193
6.6.5.3 High-Speed Universal Serial Bus (HS-USB) on Ports 1, 2, and 3 – 12-bit TLL Master
Mode.................................................................................................. 194
6.6.5.4 High-Speed Universal Serial Bus (HS-USB) on Ports 1, 2, and 3 – 8-bit TLL Master
Mode.................................................................................................. 195
6.6.6 Universal Subscriber Identity Module Interface (USIM) .................................................. 196
6.6.7 I2C Interface .................................................................................................... 198
6.6.7.1 I2C Standard/Fast-Speed Mode................................................................... 198
4 Contents
TI Internal Data — Signed NDA Required for Distribution
OMAP34xx Multimedia Device
Silicon Revision 3.0
www.ti.com SWPS034C–JUNE 2008–REVISED JULY 2008
6.6.7.2 I2C High-Speed Mode .............................................................................. 199
6.6.8 HDQ / 1-Wire Interfaces....................................................................................... 200
6.6.8.1 HDQ Protocol ........................................................................................ 200
6.6.8.2 1-Wire Protocol ...................................................................................... 201
6.6.9 UART IrDA Interface........................................................................................... 202
6.6.9.1 IrDA—Receive Mode ............................................................................... 203
6.6.9.2 IrDA—Transmit Mode............................................................................... 204
6.7 Removable Media Interfaces............................................................................................ 204
6.7.1 Memory Stick PRO (MS-PRO) Timing ...................................................................... 204
6.7.2 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing.......... 204
6.7.2.1 MMC/SD/SDIO in SD Identification Mode ....................................................... 205
6.7.2.2 MMC/SD/SDIO in High-Speed MMC Mode ..................................................... 206
6.7.2.3 MMC/SD/SDIO in Standard MMC Mode and MMC Indentification Mode ................... 209
6.7.2.4 MMC/SD/SDIO in High-Speed SD Mode ....................................................... 212
6.7.2.5 MMC/SD/SDIO in Standard SD Mode ........................................................... 215
6.8 Test Interfaces ............................................................................................................ 218
6.8.1 Embedded Trace Macro Interface (ETM)................................................................... 218
6.8.2 System Debug Trace Interface (SDTI) ...................................................................... 219
6.8.2.1 SDTI in Dual-Edge Mode .......................................................................... 219
6.8.2.2 System Debug Trace Interface in Single-Edge Mode.......................................... 219
6.8.3 JTAG Interfaces ................................................................................................ 220
6.8.3.1 JTAG – Free Running Clock Mode .............................................................. 220
6.8.3.2 JTAG – Adaptive Clock Mode ..................................................................... 222
6.8.4 cJTAG Interface ................................................................................................ 223
7 PACKAGE CHARACTERISTICS .......................................................................................... 225
7.1 Package Thermal Resistance ........................................................................................... 225
7.2 Device Nomenclature .................................................................................................... 225
7.2.1 Standard Package Symbolization............................................................................ 225
7.2.2 Variable Description Summary............................................................................... 226
7.3 Mechanical Data .......................................................................................................... 226
A GLOSSARY...................................................................................................................... 228
Important Notices ...................................................................................................................... 231

wcdma518

【文件名】:081229@52RD_OMAP34xx_ES2.0_ES2.1_POP_DM_V_J.rar
【格　式】:rar
【大　小】:2261K
【简　介】:
【目　录】:




1 INTRODUCTION ................................................................................................................. 15
2 TERMINAL DESCRIPTION.................................................................................................... 16
2.1 Terminal Assignment ...................................................................................................... 16
2.2 Ball Characteristics......................................................................................................... 17
2.3 Multiplexing Characteristics ............................................................................................... 44
2.4 Signal Description .......................................................................................................... 52
2.4.1 External Memory Interfaces .................................................................................... 52
2.4.2 Video Interfaces ................................................................................................. 56
2.4.3 Serial Communication Interfaces .............................................................................. 59
2.4.4 Removable Media Interfaces................................................................................... 66
2.4.5 Test Interfaces ................................................................................................... 67
2.4.6 Miscellaneous .................................................................................................... 68
2.4.7 General-Purpose IOs ........................................................................................... 68
2.4.8 System and Miscellaneous Terminals ........................................................................ 73
2.4.9 Power Supplies .................................................................................................. 74
3 ELECTRICAL CHARACTERISTICS........................................................................................ 76
3.1 Power Domains............................................................................................................. 76
3.2 Absolute Maximum Ratings............................................................................................... 78
3.3 Recommended Operating Conditions ................................................................................... 79
3.4 DC Electrical Characteristics ............................................................................................. 80
3.5 Core Voltage Decoupling.................................................................................................. 83
3.6 Power-up and Power-down ............................................................................................... 85
3.6.1 Power-up Sequence ............................................................................................ 85
3.6.2 Power-down Sequence ......................................................................................... 87
4 CLOCK SPECIFICATIONS.................................................................................................... 88
4.1 Input Clock Specifications................................................................................................. 89
4.1.1 Clock Source Requirements ................................................................................... 89
4.1.2 External Crystal Description.................................................................................... 89
4.1.3 Clock Squarer Input Description............................................................................... 90
4.1.4 External 32-kHz CMOS Input Clock .......................................................................... 92
4.1.5 External sys_altclk CMOS Input Clock ....................................................................... 92
4.2 Output Clock Specifications............................................................................................... 93
4.3 DPLL and DLL Specifications ............................................................................................ 94
4.3.1 Digital Phase-Locked Loop (DPLL) ........................................................................... 95
4.3.1.1 DPLL1 (MPU) ......................................................................................... 95
4.3.1.2 DPLL2 (IVA2) ......................................................................................... 95
4.3.1.3 DPLL3 (CORE)........................................................................................ 96
4.3.1.4 DPLL4 (Peripherals).................................................................................. 96
4.3.1.5 DPLL5 (Second peripherals DPLL) ................................................................ 96
4.3.2 Delay-Locked Loops (DLL)..................................................................................... 96
4.3.3 DPLLs and DLL Characteristics ............................................................................... 96
4.3.4 DPLL and DLL Noise Isolation................................................................................. 97
5 VIDEO DAC SPECIFICATIONS.............................................................................................. 99
5.1 Interface Description ..................................................................................................... 100
5.2 Electrical Specifications Over Recommended Operating Conditions .............................................. 100
5.3 Analog Supply (vdda_dac) Noise Requirements ..................................................................... 101
5.4 External Component Value Choice..................................................................................... 102
6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ............................................ 104
6.1 Timing Test Conditions................................................................................................... 104
6.2 Interface Clock Specifications........................................................................................... 104
Contents 3
TI Internal Data — Signed NDA Required for Distribution
OMAP34xx ES2.0 ES2.1
SWPS030J–SEPTEMBER 2007–REVISED MARCH 2008
6.2.1 Interface Clock Terminology.................................................................................. 104
6.2.2 Interface Clock Frequency.................................................................................... 104
6.2.3 Clock Jitter Specifications..................................................................................... 104
6.2.4 Clock Duty Cycle Error ........................................................................................ 104
6.3 Timing Parameters ....................................................................................................... 105
6.4 External Memory Interfaces ............................................................................................. 105
6.4.1 General-Purpose Memory Controller (GPMC) ............................................................. 105
6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing.............................................. 105
6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing ............................................ 114
6.4.1.3 GPMC/NAND Flash Interface Timing ............................................................ 122
6.4.2 SDRAM Controller Subsystem (SDRC)..................................................................... 126
6.4.2.1 SDRC/SDR SDRAM Interface Timing............................................................ 127
6.4.2.2 SDRC/DDR SDRAM Interface Timing............................................................ 130
6.5 Video Interfaces........................................................................................................... 144
6.5.1 Camera Interface .............................................................................................. 144
6.5.1.1 First Camera Serial Interface (CSI2) Timing .................................................... 144
6.5.1.2 Second Camera Serial Interface (CSIb) Timing................................................. 146
6.5.1.3 Parallel Camera Interface Timing ................................................................. 148
6.5.2 Display Subsystem (DSS) .................................................................................... 159
6.5.2.1 LCD Display in Bypass Mode ..................................................................... 159
6.5.2.2 LCD Display in RFBI Mode ........................................................................ 161
6.5.3 Display Serial Interface (DSI)................................................................................. 164
6.5.3.1 DSI in High-Speed Mode........................................................................... 164
6.5.3.2 DSI in Low-Power Mode and Ultralow-Power Mode ........................................... 165
6.6 Serial Communications Interfaces...................................................................................... 166
6.6.1 Multichannel Buffered Serial Port (McBSP) Timing ....................................................... 166
6.6.1.1 McBSP in Normal Mode............................................................................ 166
6.6.1.2 McBSP in TDM—Multipoint Mode (McBSP3) ................................................... 173
6.6.2 Multichannel Serial Port Interface (McSPI) Timing ........................................................ 174
6.6.2.1 McSPI in Slave Mode............................................................................... 174
6.6.2.2 McSPI in Master Mode ............................................................................. 176
6.6.3 Dual-Port Synchronous Serial Interface (SSI) Timing..................................................... 179
6.6.4 Multiport Full-Speed Universal Serial Bus (FS-USB) Interface .......................................... 181
6.6.4.1 Multiport Full-Speed Universal Serial Bus (FS-USB) – Unidirectional Standard 6-pin
Mode.................................................................................................. 182
6.6.4.2 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional Standard 4-pin
Mode.................................................................................................. 183
6.6.4.3 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional Standard 3-pin
Mode.................................................................................................. 184
6.6.4.4 Multiport Full-Speed Universal Serial Bus (FS-USB) – Unidirectional TLL 6-pin Mode ... 185
6.6.4.5 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional TLL 4-pin Mode ..... 186
6.6.4.6 Multiport Full-Speed Universal Serial Bus (FS-USB) – Bidirectional TLL 3-pin Mode ..... 188
6.6.5 Multiport High-Speed Universal Serial Bus (HS-USB) Timing ........................................... 189
6.6.5.1 High-Speed Universal Serial Bus (HS-USB) on Port 0 – 12-bit Slave Mode................ 189
6.6.5.2 High-Speed Universal Serial Bus (HS-USB) on Ports 1 and 2 – 12-bit Master Mode ..... 190
6.6.5.3 High-Speed Universal Serial Bus (HS-USB) on Ports 1, 2, and 3 – 12-bit TLL Master
Mode.................................................................................................. 191
6.6.5.4 High-Speed Universal Serial Bus (HS-USB) on Ports 1, 2, and 3 – 8-bit TLL Master
Mode.................................................................................................. 192
6.6.6 Universal Subscriber Identity Module Interface (USIM) .................................................. 193
6.6.7 I2C Interface .................................................................................................... 194
6.6.7.1 I2C Standard/Fast-Speed Mode................................................................... 195
6.6.7.2 I2C High-Speed Mode .............................................................................. 196
6.6.8 HDQ / 1-Wire Interfaces....................................................................................... 197
4 Contents
TI Internal Data — Signed NDA Required for Distribution
OMAP34xx ES2.0 ES2.1
SWPS030J–SEPTEMBER 2007–REVISED MARCH 2008
6.6.8.1 HDQ Protocol ........................................................................................ 197
6.6.8.2 1-Wire Protocol ...................................................................................... 198
6.6.9 UART IrDA Interface........................................................................................... 199
6.6.9.1 IrDA—Receive Mode ............................................................................... 200
6.6.9.2 IrDA—Transmit Mode............................................................................... 200
6.7 Removable Media Interfaces............................................................................................ 201
6.7.1 Memory Stick Pro (MS-Pro) Timing ......................................................................... 201
6.7.2 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing.......... 203
6.7.2.1 MMC/SD/SDIO in SD Identification Mode ....................................................... 204
6.7.2.2 MMC/SD/SDIO in High-Speed MMC Mode ..................................................... 206
6.7.2.3 MMC/SD/SDIO in Standard MMC Mode and MMC Indentification Mode ................... 208
6.7.2.4 MMC/SD/SDIO in High-Speed SD Mode ....................................................... 212
6.7.2.5 MMC/SD/SDIO in Standard SD Mode ........................................................... 215
6.8 Test Interfaces ............................................................................................................ 218
6.8.1 Embedded Trace Macro Interface (ETM)................................................................... 218
6.8.2 System Debug Trace Interface (SDTI) ...................................................................... 219
6.8.2.1 System Debug Trace Interface in Dual-Edge Mode............................................ 219
6.8.2.2 System Debug Trace Interface in Single-Edge Mode.......................................... 220
6.8.3 JTAG Interfaces ................................................................................................ 220
6.8.3.1 JTAG – Free Running Clock Mode .............................................................. 221
6.8.3.2 JTAG – Adaptive Clock Mode ..................................................................... 222
6.8.4 cJTAG Interface ................................................................................................ 224
7 PACKAGE CHARACTERISTICS .......................................................................................... 225
7.1 Package Thermal Resistance ........................................................................................... 225
7.2 Device Nomenclature .................................................................................................... 225
7.2.1 Standard Package Symbolization............................................................................ 225
7.2.2 Variable Description Summary............................................................................... 225
7.3 Mechanical Data .......................................................................................................... 226
A GLOSSARY...................................................................................................................... 228
Important Notices ...................................................................................................................... 231

wcdma518

上传资料很辛苦，终于传完了

dorain_wang

[em01][em01]

wcdma518

[em01][em01][em01][em01]

hpare

多谢了

firstfantasy

vC和vJ只是版本上的区别吧？

firstfantasy

怎么没有User's Manual?