【文件名】:0618@52RD_《100兆总线 时序分析法》.rar
【简 介】:
Practical timing analysis
for 100-MHz digital designs
MOST TECHNICAL LITERATURE ON HIGH-SPEED DESIGN
FOCUSES ON TERMINATION, RINGING, AND CROSSTALK.
DESPITE SIGNAL INTEGRITY’S IMPORTANCE, INADEQUATE
TIMING MARGINS CAUSE MANY MORE ERRORS IN
TODAY’S 100-MHz DIGITAL DESIGNS.
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发表于 2006-1-8 23:20:00
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