arm memory contoller PL172 spec

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供初次接触arm 内存管理的人学习
【文件名】:07914@52RD_DDI0215D_mpmc_pl172_r2p3_trm.pdf
【格　式】:pdf
【大　小】:924K
【简　介】:
【目　录】:



1 Introduction
1.1 About the PrimeCell MultiPort Memory Controller (PL172) ......................... 1-2
1.2 Supported dynamic memory devices .......................................................... 1-4
1.3 Supported static memory devices ............................................................... 1-6
1.4 Changes between r2p2 and r2p3 ................................................................ 1-7
Chapter 2 Functional Overview
2.1 MPMC functional description ...................................................................... 2-2
2.2 Overview of an example MPMC system ..................................................... 2-9
2.3 Low-power operation ................................................................................ 2-11
2.4 Locked accesses ...................................................................................... 2-13
2.5 Burst types ................................................................................................ 2-14
2.6 Busy transfer type ..................................................................................... 2-15
2.7 Arbitration .................................................................................................. 2-16
2.8 Worst-case transaction latency ................................................................. 2-18
2.9 Memory bank select .................................................................................. 2-21
Contents
iv Copyright © 2002-2004. ARM Limited. All rights reserved. ARM DDI 0215D
2.10 Memory map ............................................................................................. 2-22
2.11 Sharing memory interface signals ............................................................ 2-25
Chapter 3 Programmer’s Model
3.1 About the programmer’s model .................................................................. 3-2
3.2 Summary of registers ................................................................................. 3-3
3.3 Register descriptions .................................................................................. 3-8
Chapter 4 Programmer’s Model for Test
4.1 MPMC test harness overview ..................................................................... 4-2
4.2 Production test ............................................................................................ 4-3
4.3 Summary of test registers ........................................................................... 4-4
4.4 Test register descriptions ........................................................................... 4-5
Appendix A Signal Descriptions
A.1 AHB register signals ................................................................................... A-2
A.2 AHB memory signals .................................................................................. A-4
A.3 Miscellaneous signals ................................................................................. A-6
A.4 Pad interface and control signals ............................................................. A-10
A.5 Test Interface Controller (TIC) AHB signals ............................................. A-13
A.6 Scan test signals ...................................................................................... A-15
Appendix B Changes between Revisions r1p0 and r2p2
B.1 Functional changes .................................................................................... B-2
B.2 Performance optimizations ......................................................................... B-9
B.3 Power optimizations ................................................................................. B-10