Phase Noise and Jitter,卓联的一篇讲解.

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As clock speeds in communications systems push into the GHz range, phase noise and jitter – always key issues in analog designs – are becoming increasingly critical to the performance of digital chips and boards. Timing errors in the clock or oscillator waveforms of high-speed systems can limit the maximum speed of a digital I/O interface, increase the bit error rate of a communications link, or even cap the dynamic range of an A/D converter.
【文件名】:0611@52RD_Phase_Noise_and_Jitter_Article.pdf
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