A LOW-POWER CMOS FREQUENCY SYNTHESIZER DESIGN METHODOLOGY FOR

ohyoung

With the hardware requirements of personal and wireless
communication equipment becoming increasingly stringent, new
low power methodologies and design techniques are becoming a
necessity. One major power consuming component in front end
wireless communication systems is the phase-locked loop (PLL)
frequency synthesizer (FS). This paper details a methodology
that expands the design space exploration of CMOS PLLs to
include several FS architectures. The four FS architectures
explored here are the dual-loop PLL, fractional-N PLL, cascaded
PU (CPU),an d the DDFS architectures.
【文件名】:07420@52RD_u00780632.pdf
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