设为首页收藏本站

 找回密码
 注册
搜索
52RD研发论坛»论坛 › 硬件研发论坛(Hardware R&D Forum) › SOC芯片设计 › 这个程序报错，太奇怪了，请帮忙
返回列表 发新帖回复
查看: 677|回复: 9

[讨论] 这个程序报错，太奇怪了，请帮忙

[复制链接]
chasm
发表于 2007-1-17 11:20:06 | 显示全部楼层 |阅读模式
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity in1 is
port(
AIN:  in  std_logic_vector ( 7 downto 0 );
BIN:  in  std_logic_vector ( 7 downto 0 );
CIN:  in  std_logic_vector ( 7 downto 0 );
DIN:  in  std_logic_vector ( 7 downto 0 );
EIN:  in  std_logic_vector ( 7 downto 0 );
FIN:  in  std_logic_vector ( 7 downto 0 );
GIN:  in  std_logic_vector ( 7 downto 0 );
HIN:  in  std_logic_vector ( 7 downto 0 );
CA2: in  std_logic_vector ( 3 downto 0 );
CD2:  inout std_logic_vector ( 7 downto 0 );
CLEDBEEP:  out std_logic_vector ( 3 downto 0 );  
CDEN1D,CDEN2:  out std_logic;
CCS2,CWR2:  in  std_logic;
CDATA0,CDATA1:  in  std_logic;
CINT:  out std_logic;
clk_scan:  in std_logic);
end in1;
architecture in1_A of in1 is
SIGNAL internal_bus_out: std_logic_vector ( 3 downto 0 );
SIGNAL internal_bus_in : std_logic_vector ( 7 downto 0 );
SIGNAL internal_data : std_logic_vector (33 DOWNTO 0 );
SIGNAL dint  : std_logic;
SIGNAL temp  : std_logic;
signal  count_i  :integer range 0 to 34;
signal  count_d0 :integer range 0 to 6;
signal  count_d10 :integer range 0 to 199;
begin

  CDEN1D<='0';
  CDEN2 <='0';
  dint <= CDATA0 AND CDATA1;
  count_i <= 0;
  count_d0 <= 0;
  count_d10<= 0;
        RD:PROCESS(CCS2)
   
       BEGIN

     IF( clk_scan'event AND clk_scan='1') then
  IF(CCS2='0'AND CWR2='0') THEN
          IF(CA2="0000") THEN
               internal_bus_in<=AIN;   
     ELSIF (CA2="0001") THEN
               internal_bus_in<=BIN;
     ELSIF (CA2="0010") THEN
               internal_bus_in<=CIN;   
     ELSIF (CA2="0011") THEN
               internal_bus_in<=DIN;
      ELSIF (CA2="0100") THEN
               internal_bus_in<=EIN;
     ELSIF (CA2="0101") THEN
               internal_bus_in<=FIN;   
     ELSIF (CA2="0110") THEN
               internal_bus_in<=GIN;
     ELSIF (CA2="0111") THEN
               internal_bus_in<=HIN;                  
   
   ELSIF (CA2="1000") THEN
      internal_bus_in  <= internal_data(8 DOWNTO 1);
      
   ELSIF (CA2="1001") THEN
      internal_bus_in  <= internal_data(16 DOWNTO 9);
     
   ELSIF (CA2="1010") THEN
      internal_bus_in  <= internal_data(24 DOWNTO 17);
      
   ELSIF (CA2="1011") THEN
      internal_bus_in  <= internal_data(32 DOWNTO 25);
      CINT <= '1';
          ELSE   
      internal_bus_in<="ZZZZZZZZ";
   END IF;   
                  
   CD2<=internal_bus_in;
   END IF;
      
     END IF;  

END PROCESS;
  
WR:PROCESS(CWR2)
BEGIN
  IF( clk_scan'event AND clk_scan='1') then
   IF(CCS2='0'AND CWR2='1') THEN
   
               internal_bus_out(3 DOWNTO 0) <= CD2(3 DOWNTO 0);
      CLEDBEEP(3 DOWNTO 0)         <= internal_bus_out(3 DOWNTO 0);         
   END IF;
  END IF;              
  
END PROCESS;
COUNTD0:PROCESS(dint)
BEGIN

   if( clk_scan'event AND clk_scan='1') then
         
   IF (dint='0') THEN
   
    IF(count_d0 = 6)THEN

     count_d0  <= 0;
     count_i <= count_i+1;
     temp <= CDATA0;
    ELSE
     count_d0 <= count_d0+1;
      
    END IF;
      count_d10  <= 0;
   ELSE
    IF(count_d10 = 199)THEN
   
     count_d10  <= 0;
    -- CINT <= 'Z';
     count_i <= 0;
    -- internal_data(8 DOWNTO 1)   <= "ZZZZZZZZ";
    -- internal_data(16 DOWNTO 9)  <= "ZZZZZZZZ";
    -- internal_data(24 DOWNTO 17) <= "ZZZZZZZZ";
    -- internal_data(32 DOWNTO 25) <= "ZZZZZZZZ";
    ELSE
     count_d10 <= count_d10+1;
      
    END IF;
   count_d0 <= 0;

   END IF;
  END IF;
END PROCESS;


RINT:PROCESS(count_i)
BEGIN
         IF(count_i = 1) THEN
     internal_data(0) <= temp;
  ELSIF(count_i = 2) THEN
     internal_data(1) <= temp;
  ELSIF(count_i = 3) THEN
     internal_data(2) <= temp;        
  ELSIF(count_i = 4) THEN
     internal_data(3) <= temp;
  ELSIF(count_i = 5) THEN
     internal_data(4) <= temp;   
  ELSIF(count_i = 6) THEN
     internal_data(5) <= temp;
  ELSIF(count_i = 7) THEN
     internal_data(6) <= temp;        
  ELSIF(count_i = 8) THEN
     internal_data(7) <= temp;
  ELSIF(count_i = 9) THEN
     internal_data(8) <= temp;        
  ELSIF(count_i = 10) THEN
     internal_data(9) <= temp;
  ELSIF(count_i = 11) THEN
     internal_data(10) <= temp;
  ELSIF(count_i = 12) THEN
     internal_data(11) <= temp;
  ELSIF(count_i = 13) THEN
     internal_data(12) <= temp;      
  ELSIF(count_i = 14) THEN
     internal_data(13) <= temp;
  ELSIF(count_i = 15) THEN
     internal_data(14) <= temp;
  ELSIF(count_i = 16) THEN
     internal_data(15) <= temp;
  ELSIF(count_i = 17) THEN
     internal_data(16) <= temp;
  ELSIF(count_i = 18) THEN
     internal_data(17) <= temp;
  ELSIF(count_i = 19) THEN
     internal_data(18) <= temp;
  ELSIF(count_i = 20) THEN
     internal_data(19) <= temp;
  ELSIF(count_i = 21) THEN
     internal_data(20) <= temp;
  ELSIF(count_i = 22) THEN
     internal_data(21) <= temp;
  ELSIF(count_i = 23) THEN
     internal_data(22) <= temp;
  ELSIF(count_i = 24) THEN
     internal_data(23) <= temp;
  ELSIF(count_i = 25) THEN
     internal_data(24) <= temp;
  ELSIF(count_i = 26) THEN
     internal_data(25) <= temp;
  ELSIF(count_i = 27) THEN
     internal_data(26) <= temp;
  ELSIF(count_i = 28) THEN
     internal_data(27) <= temp;
  ELSIF(count_i = 29) THEN
     internal_data(28) <= temp;
  ELSIF(count_i = 30) THEN
     internal_data(29) <= temp;
  ELSIF(count_i = 31) THEN
     internal_data(30) <= temp;
  ELSIF(count_i = 32) THEN
     internal_data(31) <= temp;
  ELSIF(count_i = 33) THEN
     internal_data(32) <= temp;
  ELSIF(count_i = 34) THEN
     internal_data(33) <= temp;
     count_i <= 0;
        CINT <= '0';
  ELSE
     internal_data(8 DOWNTO 1)   <= "ZZZZZZZZ";
     internal_data(16 DOWNTO 9)  <= "ZZZZZZZZ";
     internal_data(24 DOWNTO 17) <= "ZZZZZZZZ";
     internal_data(32 DOWNTO 25) <= "ZZZZZZZZ";
     CINT <= 'Z';
  END IF;
   
END PROCESS;

END in1_A;
回复

使用道具 举报

chasm
 楼主| 发表于 2007-1-17 11:20:06 | 显示全部楼层 |阅读模式
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity in1 is
port(
AIN:  in  std_logic_vector ( 7 downto 0 );
BIN:  in  std_logic_vector ( 7 downto 0 );
CIN:  in  std_logic_vector ( 7 downto 0 );
DIN:  in  std_logic_vector ( 7 downto 0 );
EIN:  in  std_logic_vector ( 7 downto 0 );
FIN:  in  std_logic_vector ( 7 downto 0 );
GIN:  in  std_logic_vector ( 7 downto 0 );
HIN:  in  std_logic_vector ( 7 downto 0 );
CA2: in  std_logic_vector ( 3 downto 0 );
CD2:  inout std_logic_vector ( 7 downto 0 );
CLEDBEEP:  out std_logic_vector ( 3 downto 0 );  
CDEN1D,CDEN2:  out std_logic;
CCS2,CWR2:  in  std_logic;
CDATA0,CDATA1:  in  std_logic;
CINT:  out std_logic;
clk_scan:  in std_logic);
end in1;
architecture in1_A of in1 is
SIGNAL internal_bus_out: std_logic_vector ( 3 downto 0 );
SIGNAL internal_bus_in : std_logic_vector ( 7 downto 0 );
SIGNAL internal_data : std_logic_vector (33 DOWNTO 0 );
SIGNAL dint  : std_logic;
SIGNAL temp  : std_logic;
signal  count_i  :integer range 0 to 34;
signal  count_d0 :integer range 0 to 6;
signal  count_d10 :integer range 0 to 199;
begin

  CDEN1D<='0';
  CDEN2 <='0';
  dint <= CDATA0 AND CDATA1;
  count_i <= 0;
  count_d0 <= 0;
  count_d10<= 0;
        RD:PROCESS(CCS2)
   
       BEGIN

     IF( clk_scan'event AND clk_scan='1') then
  IF(CCS2='0'AND CWR2='0') THEN
          IF(CA2="0000") THEN
               internal_bus_in<=AIN;   
     ELSIF (CA2="0001") THEN
               internal_bus_in<=BIN;
     ELSIF (CA2="0010") THEN
               internal_bus_in<=CIN;   
     ELSIF (CA2="0011") THEN
               internal_bus_in<=DIN;
      ELSIF (CA2="0100") THEN
               internal_bus_in<=EIN;
     ELSIF (CA2="0101") THEN
               internal_bus_in<=FIN;   
     ELSIF (CA2="0110") THEN
               internal_bus_in<=GIN;
     ELSIF (CA2="0111") THEN
               internal_bus_in<=HIN;                  
   
   ELSIF (CA2="1000") THEN
      internal_bus_in  <= internal_data(8 DOWNTO 1);
      
   ELSIF (CA2="1001") THEN
      internal_bus_in  <= internal_data(16 DOWNTO 9);
     
   ELSIF (CA2="1010") THEN
      internal_bus_in  <= internal_data(24 DOWNTO 17);
      
   ELSIF (CA2="1011") THEN
      internal_bus_in  <= internal_data(32 DOWNTO 25);
      CINT <= '1';
          ELSE   
      internal_bus_in<="ZZZZZZZZ";
   END IF;   
                  
   CD2<=internal_bus_in;
   END IF;
      
     END IF;  

END PROCESS;
  
WR:PROCESS(CWR2)
BEGIN
  IF( clk_scan'event AND clk_scan='1') then
   IF(CCS2='0'AND CWR2='1') THEN
   
               internal_bus_out(3 DOWNTO 0) <= CD2(3 DOWNTO 0);
      CLEDBEEP(3 DOWNTO 0)         <= internal_bus_out(3 DOWNTO 0);         
   END IF;
  END IF;              
  
END PROCESS;
COUNTD0:PROCESS(dint)
BEGIN

   if( clk_scan'event AND clk_scan='1') then
         
   IF (dint='0') THEN
   
    IF(count_d0 = 6)THEN

     count_d0  <= 0;
     count_i <= count_i+1;
     temp <= CDATA0;
    ELSE
     count_d0 <= count_d0+1;
      
    END IF;
      count_d10  <= 0;
   ELSE
    IF(count_d10 = 199)THEN
   
     count_d10  <= 0;
    -- CINT <= 'Z';
     count_i <= 0;
    -- internal_data(8 DOWNTO 1)   <= "ZZZZZZZZ";
    -- internal_data(16 DOWNTO 9)  <= "ZZZZZZZZ";
    -- internal_data(24 DOWNTO 17) <= "ZZZZZZZZ";
    -- internal_data(32 DOWNTO 25) <= "ZZZZZZZZ";
    ELSE
     count_d10 <= count_d10+1;
      
    END IF;
   count_d0 <= 0;

   END IF;
  END IF;
END PROCESS;


RINT:PROCESS(count_i)
BEGIN
         IF(count_i = 1) THEN
     internal_data(0) <= temp;
  ELSIF(count_i = 2) THEN
     internal_data(1) <= temp;
  ELSIF(count_i = 3) THEN
     internal_data(2) <= temp;        
  ELSIF(count_i = 4) THEN
     internal_data(3) <= temp;
  ELSIF(count_i = 5) THEN
     internal_data(4) <= temp;   
  ELSIF(count_i = 6) THEN
     internal_data(5) <= temp;
  ELSIF(count_i = 7) THEN
     internal_data(6) <= temp;        
  ELSIF(count_i = 8) THEN
     internal_data(7) <= temp;
  ELSIF(count_i = 9) THEN
     internal_data(8) <= temp;        
  ELSIF(count_i = 10) THEN
     internal_data(9) <= temp;
  ELSIF(count_i = 11) THEN
     internal_data(10) <= temp;
  ELSIF(count_i = 12) THEN
     internal_data(11) <= temp;
  ELSIF(count_i = 13) THEN
     internal_data(12) <= temp;      
  ELSIF(count_i = 14) THEN
     internal_data(13) <= temp;
  ELSIF(count_i = 15) THEN
     internal_data(14) <= temp;
  ELSIF(count_i = 16) THEN
     internal_data(15) <= temp;
  ELSIF(count_i = 17) THEN
     internal_data(16) <= temp;
  ELSIF(count_i = 18) THEN
     internal_data(17) <= temp;
  ELSIF(count_i = 19) THEN
     internal_data(18) <= temp;
  ELSIF(count_i = 20) THEN
     internal_data(19) <= temp;
  ELSIF(count_i = 21) THEN
     internal_data(20) <= temp;
  ELSIF(count_i = 22) THEN
     internal_data(21) <= temp;
  ELSIF(count_i = 23) THEN
     internal_data(22) <= temp;
  ELSIF(count_i = 24) THEN
     internal_data(23) <= temp;
  ELSIF(count_i = 25) THEN
     internal_data(24) <= temp;
  ELSIF(count_i = 26) THEN
     internal_data(25) <= temp;
  ELSIF(count_i = 27) THEN
     internal_data(26) <= temp;
  ELSIF(count_i = 28) THEN
     internal_data(27) <= temp;
  ELSIF(count_i = 29) THEN
     internal_data(28) <= temp;
  ELSIF(count_i = 30) THEN
     internal_data(29) <= temp;
  ELSIF(count_i = 31) THEN
     internal_data(30) <= temp;
  ELSIF(count_i = 32) THEN
     internal_data(31) <= temp;
  ELSIF(count_i = 33) THEN
     internal_data(32) <= temp;
  ELSIF(count_i = 34) THEN
     internal_data(33) <= temp;
     count_i <= 0;
        CINT <= '0';
  ELSE
     internal_data(8 DOWNTO 1)   <= "ZZZZZZZZ";
     internal_data(16 DOWNTO 9)  <= "ZZZZZZZZ";
     internal_data(24 DOWNTO 17) <= "ZZZZZZZZ";
     internal_data(32 DOWNTO 25) <= "ZZZZZZZZ";
     CINT <= 'Z';
  END IF;
   
END PROCESS;

END in1_A;
回复

使用道具 举报

chasm
 楼主| 发表于 2007-1-17 11:21:06 | 显示全部楼层
出错：

@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(7) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(6) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(5) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(4) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(3) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(2) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(1) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(0) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":36:9:36:16|Multiple non-tristate drivers for net count_d0(2) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":36:9:36:16|Multiple non-tristate drivers for net count_d0(1) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":36:9:36:16|Multiple non-tristate drivers for net count_d0(0) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(5) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(4) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(3) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(2) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(1) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(0) in in1
点评回复

使用道具 举报

chasm
 楼主| 发表于 2007-1-17 11:32:51 | 显示全部楼层
我用的是Lattice M0的芯片，要做一个8组8位输入信号，一组4位输出信号，两个维根信号转换成并行信号出处，外接了一个有源晶振，可分频得到脉冲信号。
定义如下的计数信号，为何出错：
        signal  count_i        :integer range 0 to 34;
        signal  count_d0        :integer range 0 to 6;
        signal  count_d10        :integer range 0 to 199;

不知道为什么会出错，请高手指教。
点评回复

使用道具 举报

llkhbwh
发表于 2007-1-17 12:43:04 | 显示全部楼层
我也想知道，
帮你顶起，等待高手～～！[em08][em08][em08]
点评回复

使用道具 举报

LostKid
发表于 2007-1-19 09:22:55 | 显示全部楼层
我觉得可能是综合的软件需要设置一下
只是我的猜测,我没有用过Lattice的东东
点评回复

使用道具 举报

chasm
 楼主| 发表于 2007-1-17 11:21:06 | 显示全部楼层
出错：

@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(7) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(6) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(5) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(4) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(3) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(2) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(1) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":37:9:37:17|Multiple non-tristate drivers for net count_d10(0) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":36:9:36:16|Multiple non-tristate drivers for net count_d0(2) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":36:9:36:16|Multiple non-tristate drivers for net count_d0(1) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":36:9:36:16|Multiple non-tristate drivers for net count_d0(0) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(5) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(4) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(3) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(2) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(1) in in1
@E: CL219 :"D:\arm\cpld\test\in\mz32c.vhd":35:9:35:15|Multiple non-tristate drivers for net count_i(0) in in1
点评回复

使用道具 举报

chasm
 楼主| 发表于 2007-1-17 11:32:51 | 显示全部楼层
我用的是Lattice M0的芯片，要做一个8组8位输入信号，一组4位输出信号，两个维根信号转换成并行信号出处，外接了一个有源晶振，可分频得到脉冲信号。
定义如下的计数信号，为何出错：
        signal  count_i        :integer range 0 to 34;
        signal  count_d0        :integer range 0 to 6;
        signal  count_d10        :integer range 0 to 199;

不知道为什么会出错，请高手指教。
点评回复

使用道具 举报

llkhbwh
发表于 2007-1-17 12:43:04 | 显示全部楼层
我也想知道，
帮你顶起，等待高手～～！[em08][em08][em08]
点评回复

使用道具 举报

LostKid
发表于 2007-1-19 09:22:55 | 显示全部楼层
我觉得可能是综合的软件需要设置一下
只是我的猜测,我没有用过Lattice的东东
点评回复

使用道具 举报

返回列表 发新帖 回复
高级模式
B Color Image Link Quote Code Smilies

本版积分规则

Archiver|手机版|小黑屋|52RD我爱研发网 ( 沪ICP备2022007804号-2 )

GMT+8, 2024-11-24 08:59 , Processed in 0.046472 second(s), 16 queries , Gzip On.

Powered by Discuz! X3.5

© 2001-2023 Discuz! Team.

快速回复 返回顶部 返回列表