Power PC 处理器 440EPx，高端处理器。

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Technical Specifications
440 processor core with 32K instruction cache/32K data cache
CoreConnect™ bus architecture
Up to 667MHz performance and Up to 1,334 DMIPS
USB 2.0 Host and Device Controllers with on-board PHY
5 stage FPU with 2.0 MFLOPS/MHz
16KB On-Chip Memory (OCM)
Kasumi encryption/decryption engine
Turbo Security Engine:
Optional on-chip IPSec/SSL security acceleration engine
32/16/8-bit data, 30-bit address External Peripheral Bus
supporting ROM, EPROM, SRAM, Flash and Slave peripheral I/O
banks including support for NAND Flash
Two 10/100/1G Ethernet MACs with SGMII
32-bit PCI controller, 66MHz (PCI v2.2 compliant)
32/64-bit DDR1/2 SDRAM controller with ECC support
32-bit, 83MHz On-chip Peripheral Bus
Programmable Interrupt Controller with 10 external inputs
On-chip Peripherals including:
Four serial ports
Two IIC controllers
One SPI Serial Communications Port (SCP)
Up to 53 general purpose I/Os
Target Applications
Imaging
Industrial Control
Networking
【文件名】:061230@52RD_PPC440EPx_DS2023_v1_15.pdf
【格　式】:pdf
【大　小】:1602K
【简　介】:
【目　录】: