MT6225和MT6226有什么区别？

tomfeng

<DIV class=quote><B>以下是引用<I>aquasnake</I>在2007-1-29 14:56:29的发言：</B>



通常ARM7的KeyScan一定是软件的:
首先在外部循环跑KeyScan,如果是8X4的键盘距阵,8跟出线(Strobe线,也叫列线),4跟进线(Return线,也叫行线),进线Return是带中断触发的,但是此低电平的给出是要Strobe线不断轮流循环置0的,虽然键盘中断识别键值是用中断来做,但是KeyScan还是得软件不断去刷Strobe出线.不管任务忙或者闲
当然在播放MP4时也可以降低flush key(key scan)的频率,这样软件smart些,但操作有些须迟钝,况且一般DH根本不会涉及此底层</DIV>


  键盘扫描从功能块上包括两块：1－是否有键盘按下 2－按下的是哪个键 因此平常只要将输出全为低，开启输入中断就可以了。有中断再判断是哪个键按下。 3－键盘释放 。。。。
  因此不太会出现键盘中断被定时反复调用。（除非有键盘按下，启动延时防抖动）。

tarenasoft

楼上几们是高手啊，多多讨论

blazer007

高手讨论就是 “强”
顶        ！！！！！

ada981200

对哦 ,在ti平台上 就是纯软件扫描,但mtk上好像是器件做好的,软件只需要去读寄存器就好了.

BrayL

The MT6225 is a highly integrated single chip solution for
GSM/GPRS phone. Based on 32-bitARM7EJ-STM RISC
processor, MT6225 features not only high performance
GPRS Class 12 MODEM but is also designed with support
for the wireless multi-media applications, such as
advanced display engine, synthesis audio with 64-tone
polyphony, digital audio playback, Java acceleration,
MMS and etc. Additionally, MT6225 provides varieties of
advanced interfaces for functionality extensions, like
3-port external memory interface, 3-port 8/16-bit parallel
interface, NAND Flash, IrDA, USB and MMC/SD/MS/MS
Pro. The typical application can be shown as Figure 1.
Platform
MT6225 is capable of running the ARM7EJ-STM RISC
processor at up to 104 MHz, thus providing fast data
processing capabilities. In addition to the high clock
frequency, a separate CODE cache is also added to further
improve the overall system efficiency.
For large amounts of data transfer, high performance DMA
(Direct Memory Access) with hardware flow control is
implemented, which greatly enhances the data movement
speed while reducing MCU processing load.

External Memory Interface

To provide the greatest capacity for expansion and
maximum bandwidth for data intensive applications such
as multimedia features, MT6225 supports up to 3 external
state-of-the-art devices through its 8/16-bit host interface.
High performance devices such as Mobile RAM and
Cellular RAM are supported for maximum bandwidth.
Traditional devices such as burst/page mode flash, page
mode SRAM, and Pseudo SRAM are also supported. For
greatest compatibility, the memory interface can also be
used to connect to legacy devices such as Color/Parallel
LCD, and multi-media companion chips are all supported
through this interface. To minimize power consumption
and ensure low noise, this interface is designed for flexible
I/O voltage and allows lowering of the supply voltage
down to 1.8V. The driving strength is configurable for
signal integrity adjustment. The data bus also employs
retention technology to prevent the bus from floating
during a turn over.

Multi-media Subsystem

In order to provide more flexibility and bandwidth for
multi-media products, an additional 8/16 bit parallel
interface is incorporated. This interface is designed
specially for support with Camera companion chip as well
as LCD panel. In addition, MT6225 has camera YUV
interface that can connect to CMOS sensor of resolution up
to VGA. Moreover, it can connect NAND flash device to
provide a solution for multi-media data storage. For
running multi-media application faster, MT6225 integrates
also several hardware-based engines. With hardware based
Resizer and advanced display engine, it can display and
combine arbitrary size of images with up to 4 blending
layers.

User Interface

For user interactions, the MT6225 brings together all
necessary peripheral blocks for multi-media GSM/GPRS
phone. It comprises the Keypad Scanner with capability of
multiple key pressing, SIM Controller, Alerter, Real Time
Clock, PWM, Serial LCD Controller and General Purpose
Programmable I/Os. For connectivity and data storage, the
MT6225 consists of UART, IrDA, USB 1.1 Slave, SDIO
and MMC/SD/MS/MS Pro.

Audio Interface

Using a highly integrated mixed-signal Audio Front-End,
the MT6225 architecture allows for easy audio interfacing
with direct connection to the audio transducers. The audio
interface integrates D/A and A/D Converters for Voice
band, as well as high resolution Stereo D/A Converters for
Audio band. In addition, MT6225 also provides Stereo
Input and Analog Mux.
MT6225 supportsAMR codec to adaptively optimize
speech and audio quality. Moreover, HE-AAC codec is
implemented to deliver CD-quality audio at low bit rates.
Overall, MT6225’s audio features provide a rich platform
for multi-media applications.

Radio Interface

MT6225 integrates a mixed-signal Baseband front-end in
order to provide a well-organized radio interface with
flexibility for efficient customization. It contains gain and

offset calibration mechanisms, and filters with
programmable coefficients for comprehensive
compatibility control on RF modules. This approach also
allows the usage of a high resolution D/A Converter for
controlling VCXO or crystal, thus reducing the need for
expensive TCVCXO. MT6225 achieves great MODEM
performance by utilizing 14-bit high resolution A/D
Converter in the RF downlink path. Furthermore, to reduce
the need for extra external current-driving component, the
driving strength of some BPI outputs is designed to be
configurable.

Debug Function

The JTAG interface enables in-circuit debugging of
software program with the ARM7EJ-S core. With this
standardized debugger interface, the MT6225 provides
developers with a wide set of options for choosing ARM
development kits from supports of thirty parties. For
security reason, JTAG interface can be disabled by
programming internal OTP (one-time programmable) fuse.
Power Management
The MT6225 offers various low-power features to help
reduce system power consumption. These features include
Pause Mode of 32KHz clocking at Standby State, Power
Down Mode for individual peripherals, and Processor
Sleep Mode. In addition, MT6225 is also fabricated in
advanced low leakage CMOS process, hence providing an
overall ultra low leakage solution.
Package
The MT6225 device is offered in a 12mm×12mm, 264-ball,
0.65 mm pitch, TFBGA package.

BrayL

6225 Platform Feature
? General
? Integrated voice-band, audio-band and base-band
analog front ends
? TFBGA 12mm×12mm, 264-ball, 0.65 mm pitch
package
? MCU Subsystem
? ARM7EJ-S 32-bit RISC processor
? High performance multi-layer AMBA bus
? Java hardware acceleration for fast Java-based
games and applets
? ARM7EJ-S Operating frequency: 26/52/104 MHz
? Dedicated DMA bus
? 14 DMA channels
? 48K Bytes on-chip SRAM
? 72K Bytes MCU dedicated Tightly Coupled
Memory
? 16K Bytes Code cache
? On-chip boot ROM for Factory Flash
Programming
? Watchdog timer for system crash recovery
? 2 sets of General Purpose Timer
? Circuit Switch Data coprocessor
? Division coprocessor
? External Memory Interface
? Supports up to 3 external devices
? Supports 8-bit or 16-bit memory components with
maximum size of up to 64M Bytes each
? Supports Mobile RAM and Cellular RAM
? Supports Flash and SRAM with Page Mode or
Burst Mode
? Supports Pseudo SRAM
? Industry standard Parallel LCD Interface
? Supports multi-media companion chips with 8/16
bits data width
? Flexible I/O voltage of 1.8V ~ 2.8V for memory
interface
? Configurable driving strength for memory
interface
? User Interfaces
? 6-row × 7-column keypad controller with
hardware scanner
? Supports multiple key presses for gaming
? SIM/USIM Controller with hardware T=0/T=1
protocol control
? Real Time Clock (RTC) operating with a separate
power supply
? General Purpose I/Os (GPIOs)
? 2 Sets of Pulse Width Modulation (PWM) Output
? Alerter Output with Enhanced PWM or PDM
? 4~10 external interrupt lines
? Connectivity
? 3 UARTs with hardware flow control and speed up
to 921600 bps
? IrDA modulator/demodulator with hardware
framer supports SIR mode of operation
? Full-speed USB 1.1 Device controller
? Multi Media Card/Secure Digital Memory
Card/Memory Stick/Memory Stick Pro host
controller
? Supports SDIO interface for SDIO peripherals as
well as WIFI connectivity
? DAI/PCM and I2S interface for Audio application
? Security


? Supports security key for code protection
? 143-bit unique/secret chip ID
? Power Management
? Power Down Mode for analog and digital circuits
? Processor Sleep Mode
? Pause Mode of 32KHz clocking at Standby State
? 7-channel Auxiliary 10-bit A/D Converter for
charger and battery monitoring and photo sensing
? Test and Debug
? Built-in digital and analog loop back modes for
both Audio and Baseband Front-End
? DAI port complying with GSM Rec.11.10
? JTAG port for debugging embedded MCU


1.2 MODEM Features
? Radio Interface and Baseband Front End
? GMSK modulator with analog I and Q channel
outputs
? 10-bit D/A Converter for uplink baseband I and Q
signals
? 14-bit high resolution A/D Converter for downlink
baseband I and Q signals
? Calibration mechanism of offset and gain
mismatch for baseband A/D Converter and D/A
Converter
? 10-bit D/A Converter forAutomatic Power
Control
? 13-bit high resolution D/A Converter for
Automatic Frequency Control
? Programmable Radio RX filter
? 2 Channels bi-directional Baseband Serial
Interface (BSI) with 3-wire or 4-wire control
? 10-Pin Baseband Parallel Interface (BPI) with
programmable driving strength
? Multi-band support
? Voice and Modem CODEC
? Dial tone generation
? Voice Memo
? Noise Reduction
? Echo Suppression / Echo Cancellation
? Advanced Sidetone Oscillation Reduction
? Digital sidetone generator with programmable
gain
? Two programmable acoustic compensation filters
? GSM/GPRS quad vocoders for adaptive multirate
(AMR), enhanced full rate (EFR), full rate (FR)
and half rate (HR)
? FR error concealment
? GSM channel coding, equalization and A5/1, A5/2
and A5/3 ciphering
? GPRS GEA1, GEA2 and GEA3 ciphering
? Programmable GSM/GPRS Modem
? Packet Switched Data with CS1/CS2/CS3/CS4
coding schemes
? GSM Circuit Switch Data
? GPRS Class 12
? Voice Interface and Voice Front End
? Two microphone inputs sharing one low noise
amplifier with programmable gain and automatic
gain control (AGC) mechanism
? Voice power amplifier with programmable gain
? 2nd order Sigma-Delta A/D Converter for voice
uplink path
? D/A Converter for voice downlink path
? Supports half-duplex hands-free operation
? Compliant with GSM 03.50


1.3 Multi-Media Features
? LCD/NAND Flash Interface
? 18-bit Parallel Interface supports 8/16 bit NAND
flash and 8/9/16/18 bit Parallel LCD
? 8/16 bit NAND Flash Controller with 1-bit ECC
correction for mass storages
? 2 Chip selects available for high-density NAND
flash device
? Serial LCD Interface with 8/9 bit format support
? LCD Controller
? Hardware accelerated display
? Supports simultaneous connection to up to 2
parallel LCD and 1 serial LCD modules
? Supports format: RGB332, RGB444, RGB565,
RGB666, RGB888
? Supports LCD panel maximum resolution up to
800x600 at 16bpp
? Supports hardware display rotation
? Capable of combining display memories with up to
4 blending layers
? Accelerated Gamma correction with
programmable gamma table.
? Image Signal Processor
? 8 bit YUV format image input
? Capable of processing image of size up to VGA
? Flexible I/O voltage of 1.8V ~ 2.8V
? Audio CODEC
? Wavetable synthesis with up to 64 tones
? Advanced stereo wavetable synthesizer
? Wavetable including GM full set of 128
instruments and 47 sets of percussions
? PCM Playback and Record
? Digital Audio Playback
? HE-AAC decode support
? Audio Interface and Audio Front End
? Supports I2S interface
? High resolution D/A Converters for Stereo Audio
playback
? Stereo analog input for stereo audio source
? Analog multiplexer for Stereo Audio
? Stereo to Mono Conversion
? FM radio recording


1.4 General Description
Figure 2 details the block diagram of MT6225. Based on dual-processor architecture, the major processor of MT6225
is ARM7EJ-S, which mainly runs high-level GSM/GPRS protocol software as well as multi-media applications. With
the other one is a digital signal processor corresponding for handling the low-level MODEM as well as advanced audio
functions. Except for some mixed-signal circuitries, the other building blocks in MT6225 are connected to either the
microcontroller or the digital signal processor. Specifically, MT6225 consists of the following subsystems:
? Microcontroller Unit (MCU) Subsystem, including an ARM7EJ-S RISC processor and its accompanying
memory management and interrupt handling logics.
? Digital Signal Processor (DSP) Subsystem, including a DSP and its accompanying memory, memory
controller, and interrupt controller.
? MCU/DSP Interface, where the MCU and the DSP exchange hardware and software information.
? Microcontroller Peripherals, which include all user interface modules and RF control interface modules.
? Microcontroller Coprocessors, which intend to run computing-intensive processes in place of Microcontroller.
? DSP Peripherals, which are hardware accelerators for GSM/GPRS channel codec.
? Multi-media Subsystem, which integrate several advanced accelerators to support multi-media applications.
? Voice Front End, the data path of conveying analog speech from and to digital speech.
? Audio Front End, also the data path of conveying stereo audio from stereo audio source
? Baseband Front End, the data path of conveying digital signal from and to analog signal of RF modules.
? Timing Generator, generating the control signals related to the TDMA frame timing.
? Power, Reset and Clock subsystem, managing the power, reset and clock distribution inside MT6225.
Details of the individual subsystems and blocks are described in following Chapters.