Motorola MCore User Manual

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This manual is intended for system software developers and applications programmers
who want to develop products for M•CORE-based microcontroller systems. It is
assumed that the reader understands operating systems, microprocessor and microcontroller
system design, and the basic principles of RISC processing.
1.1 Features ............1-1
1.2 Microarchitecture Summary ....1-2
1.3 Programming Model .........1-3
1.4 Data Format Summary ............1-4
1.5 Operand Addressing Capabilities .....1-5
1.6 Instruction Set Overview ...........1-6
SECTION 2 REGISTERS
2.1 User Programming Model ............2-1
2.1.1 General-Purpose Registers ...2-1
2.1.2 Program Counter ...................2-2
2.1.3 Condition Code/Carry Bit .......2-2
2.2 Supervisor Programming Model ....2-2
2.2.1 Alternate Register File ...........2-3
2.2.2 Processor Status Register .....2-4
2.2.2.1 Updates to the PSR .......-6
2.2.2.2 Exception Recognition and
2.2.2.3 RTE and RFI Instruction Updates ..2-7
2.2.2.4 MTCR Instruction Updates .............2-7
2.2.3 Vector Base Register .........2-7
2.2.4 Supervisor Storage Registers ....2-7
2.2.5 Exception Shadow Registers .....2-7
2.2.6 Global Control Register .....2-8
2.2.7 Global Status Register .....2-8
SECTION 3 INSTRUCTIONS
3.1 Instruction Types and Addressing Modes ....3-1
3.1.1 Register-to-Register Instructions ......3-1
3.1.1.1 Monadic Register Addressing Mode ..3-1
3.1.1.2 Dyadic Register Addressing Mode .....3-1
3.1.1.3 Register with 5-Bit Immediate Mode ...3-2
3.1.1.4 Register with 5-Bit Offset Immediate Mode ....3-2
3.1.1.5 Register with 7-Bit Immediate Mode ....3-2
3.1.1.6 Control Register Addressing Mode ...3-3
3.1.2 Data Memory Access Instructions .....3-3
3.1.2.1 Scaled 4-Bit Immediate Addressing Mode ..3-3
3.1.2.2 Load/Store Register Quadrant Mode ..3-3
3.1.2.3 Load/Store Multiple Register Mode .....3-3
3.1.2.4 Load Relative Word Mode ......3-4
3.1.3 Flow Control Instructions .....3-4
3.1.3.1 Scaled 11-Bit Displacement Mode ...3-4
3.1.3.2 Register Addressing Mode ......3-4
3.1.3.3 Indirect Mode .....3-5
3.1.3.4 Register with 4-Bit Negative Displacement Mode ...3-5
3.2 Opcode Map ......3-6
3.3 Instruction Set ...3-9
SECTION 4 EXCEPTION PROCESSING
4.1 Exception Processing Overview ...4-1
4.2 Stages of Exception Processing ...4-2
4.3 Exception Vectors ..4-3
4.4 Exception Types .....4-4
4.4.1 Reset Exception (Vector Offset 0x0) ....4-4
4.4.2 Misaligned Access Exception (Vector Offset 0x4) ..4-4
4.4.3 Access Error Exception (Vector Offset 0x8) ....4-5
4.4.4 Divide-by-Zero Exception (Vector Offset 0x0C) .......4-5
4.4.5 Illegal Instruction Exception (Vector Offset 0x10) ..4-5
4.4.6 Privilege Violation Exception (Vector Offset 0x14) .4-5
4.4.7 Trace Exception (Vector Offset 0x18) ........4-5
4.4.8 Breakpoint Exception (Vector Offset 0x1C).4-6
4.4.9 Unrecoverable Error Exception (Vector Offset 0x20) ......4-7
4.4.10 Soft Reset Exception (Vector Offset 0x24) ..4-7
4.4.11 Interrupt Exceptions ......4-7
4.4.11.1 Normal Interrupt (INT) ..4-8
4.4.11.2 Fast Interrupt (FINT) ....4-8
4.4.12 Hardware Accelerator Exception (Vector Offset 0x30).....4-8
4.4.13 Instruction Trap Exception (Vector Offset 0x40-0x5C......4-9
4.5 Exception Priorities .......4-9
4.6 Returning from Exception Handlers .....4-11


【文件名】:061017@52RD_mcore_manual.pdf
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