Basic ESD And IO Design（共315页）

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主要集中讨论IC设计中使用的防ESD的方法，layout的注意要点，IO接口设计，固定电压ESD，失效模式分析等。全文九大章节，共315页，内容极为翔实。为影印版英文，具体不多加介绍。
有点缺钱，黑心收1元。
小附目录一段：
L.7  Y,, to- V} Core Clamps 161
2.7.1.  MDS Hased / 61
2.7.2.  Diode Clamps/ 62
2.7.3.  Cantilevered Diode / 68
2.8_ CDM Guidelines / 71
2.9. Summary / 79
Referencm J SO
ADDITIONAL ESO CON 51OCRATION5
3.1
3.2
Capacitor Bm6ts in Stress Reduction / 81
Packaging Effects oil ESA / 86
3.2.1.  Conventional Packaging J 86
3.2.2.  MU1tichip Modules / 90
Small-Chip ESD issues 1 93
Benefits of Distributed Clamps / 95
Predriver Designs / 96
3.3.
3.4.
3.5
3.6.   Antenna Diode Issues / 99
3.7.  Hot-Electron Interactions f 103
3.8.  Latchup Issues / l05
3.9.  Silicon-on-Insulator ESD Protection / 107
3.10. Summary / 109
References / 110
4.1 D. Digital Compensation / 158
4.11. Frequency-Based Compensation / 161
4.12. Simultaneous Switching Output Naise / 162
4.12.1_ Design for SSO Reduction / 168
4.12.1.1.  Predriver Skewing / 16&
4.12_1.2.  NP-Inverted Stack Driver / 169
4.12.1.3.  DlfererdW Signaling ,' 172
4.12.1.4.  SSO Reduction Using Packaging
Options / 172
4.12.1.5.  SSO Reduction Using Loii-Weigi
Coding / 173
4.13. System Modeling / 174
4.14. IJO lnfarmation on the Internet / 178
4.15_ Summary / 174
References } 180
COM,6N,
LAYOUT Issues
5.1.  Output Transistor Layout J 133
5.2,  Thick-Field Oxide (TFO) Layout / 19
5.3.  Diode Layout / 191
5.4.  Decoupling Capacitors / 192
5.5.  SCR Layout ) 196
5.5.  Antenna Diode Layout j 197
5.7.  Resistor Layouts / 197
5.8.  Periphery Layout / 202
5.8.1.  Power Delivery / 2112
5.8.2   IJo Routing Channels / 206
5_9.  Metal Design [;uses J 207
5.10. PSD Layout Verificatiou ! 212
5.10.1. Manual PSD Veri&catiox
5.10_2. Automated Verification
5.11. Summary / 213
References 1 214
eso near 110 INTERACTIONS
6-1. V0 Pcifotxnance Trade-off 1 219
6.1.1-  impact on Output Buffer
6-1.2,  Impact on Compensation
Implementation 1 220
Input Pass Transistor Jitters
OthcrInleractions / 224
rv Noise Cannon. ;nfn !'n,n
rln
Snpvlics r z26
120 and Corc Switching Current
Characterisrirc 1 '177
Peripheral Noise Coupling ThrouSf
FSn no-l- ) iie
5.2.3.  Peripheral IYoiss anc
Lnterartinn 1 711
Power System imvcdarnca
ESD Diodes and I/4 Signal Integrity / 233
6.3.1.  High-Frequency Leakage in LJD f 24:
6.3
R} }ow.ee  17A.
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MIXED-VOLTAQ6 ESD                           2-
7.1,       Mixed-Voltage Input Design 1 246
7.1.1.  Input Design for Low-VOSWE Core and
High-Voltage 1/O / 246
7,1,2_  Input Design far High-Voltage Core and
Low-Voltage 1/0 17.55
7.1.3.  Capacidve-COUpled Input Receiver / 7.56
7.2.  Output Design for Mixed Voltage j 257
7.2_ L  Opcn-Dwain Design for High-Voltage 110 / 258
7,2,2.  CMOS Buffcr Design for Higb-Voltage 1/O 1260
7.2.3.  Output Predrirars for High-Voltage 1/O 1 263
7,3-  Effect on power Supply Coupling Diodes 1 264
7.4.  Separate FSD Bus j 266
7.5.  Back Biasing / 269
7.6.  Process Modifications to Support High Voltages / 272
7.7.  Summary / 273

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