SHARC DSP

kevin_liao

【文件名】:06724@52RD_1013362339ADSP_TS202S_a.pdf
【格　式】:pdf
【大　小】:2591K
【简　介】: The TigerSHARC DSP uses a Static SuperscalarTM† architecture.
This architecture is superscalar in that the ADSP-TS202S processor’s
core can execute simultaneously from one to four 32-bit
instructions encoded in a very large instruction word (VLIW)
instruction line using the DSP’s dual compute blocks. Because
the DSP does not perform instruction reordering at runtime—
the programmer selects which operations will will execute in parallel
prior to runtime—the order of instructions is static.
【目　录】: