Writing Testbenches Using SystemVerilog,Welcome to join

kingkun1205 · 发表于 2006-6-8 14:38:00

System verilog is becoming the most popular next generation verification and rtl design HDL. It is compatible to Verilog2001 and extendable verilog.
Welcome to join in discussion!

kingkun1205 · 发表于 2006-6-8 14:39:00

<P>Ask Admin to put it on the top.</P><P>thanks</P>

eyege · 发表于 2006-6-11 20:13:00

[em01]初级阶段是一个不错的选择

dewatdawn · 发表于 2006-8-18 20:25:00

什么意思？我还以为《Writing Testbench》出新版本了呢

feiying_cq · 发表于 2006-9-22 14:21:00

很多都用synopsys的VERA做验证哦

hent_yang · 发表于 2006-11-10 21:38:00

如果有足够的钱E可能更好用

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[讨论] Writing Testbenches Using SystemVerilog,Welcome to join