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【文件名】:0665@52RD_Verilog-XL Reference[1].part01.rar
【格 式】:rar
【大 小】:500K
【简 介】:No part of this publication may be reproduced in whole or in part by any means (including photocopying or storage in an information storage/retrieval system) or transmitted in any form or by any means without prior written permission from Cadence Design Systems, Inc. (Cadence).
Information in this document is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s
customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.
【目 录】:
1 Introduction
2 Lexical Conventions
3 Data Types
4 Expressions
5 Assignments
6 Gate and Switch Level Modeling
7 User-Defined Primitives (UDPs)
8 Behavioral Modeling
9 Tasks and Functions
10 Disabling of Named Blocks and Tasks
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发表于 2006-6-5 13:06:00
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