EMC in PWB design by Matti Uusimäki (NOKIA)

seymour

【文件名】:06529@52RD_Emc_pwb.ppt
【格　式】:ppt
【大　小】:3305K
【简　介】:
Minimize noise generating structures
- noisy lines should be short (fast busses, TX RF output line, etc)
- Avoid loop structures (TX current loop…where is the return current)
- Fast Rising edge of digital signal generates a LOT of noise
Optimize sensitive lines
- keep differential signals balanced
- route them through the 'quiet' areas
- use 'coaksial' structure if very sensitive (gnd-signal-gnd, and lot of vias)
- Check the parallel layers (up to next gnd layer) that no noisy signals
- don't make loop structures
- Check signal and return current loop (they should be small) no noisy signals through this loop
Make sure that you haven't cut gnd layer in pieces
Connect all floating area fills to gnd
Consult EMC designer during the first component placement

【目　录】:
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