Morgan Kaufmann - Asic & Fpga Verification - A Guide To Component Modelin

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【文件名】:06524@52RD_Morgan Kaufmann - Asic & Fpga Verification - A Guide To Component Modeling - 2005.rar
【格　式】:rar
【大　小】:1415K
【简　介】:Digital electronic designs continue to evolve toward more complex, higher pincount
components operating at higher clock frequencies. This makes debugging board
designs in a lab with a logic analyzer and an oscilloscope considerably more difficult
than in the past. This is because signals are becoming physically more difficult to
probe and because probing them is more likely to change the operation of the circuit.
Much of the custom logic in today’s products is designed into ASICs or FPGAs.
Although this logic is usually verified through simulation as a standard part of
the design process, the interfaces to standard components on the board, such as
memories and digital signal processors, often go unsimulated and are not verified
until a prototype is built.
Waiting to test for problems this late in the design process can be expensive,
however. In terms of both time and resources, the costs are higher than performing
up-front simulation. The decision not to do up-front board simulation usually
centers around a lack of models and methodology. In ASIC and FPGA Verification:
A Guide to Component Modeling, we address both of these issues.
【目　录】:

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