【上海】-Analog/Mixed Signal IC Design Opportunities（SerDES）

sophia_miya

The right candidate must have demonstrated experience in SerDes transceiver designs including some of the following circuit blocks: System level modeling by matlab, C, or VerilogA; Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; Voltage Regulators.  Candidate should have working knowledge of a set of common SerDes standards and their electrical requirements, and a thorough understanding of jitter. Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification (Cadence tool experience, lab test experience, and experience at 65nm and below technologies are a plus).  

Job Requirements:
•         BSEE [MSEE/Ph.D EE preferred]
•         Minimum 5 years experience in CMOS SerDes IC design