VLSI handbook:PLL circuits

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【文件名】:06517@52RD_CHP57 PLL circuits.rar
【格　式】:rar
【大　小】:835K
【简　介】:Phase-locked loop
(PLL) is a circuit architecture that causes a particular system to track with another one.More precisely, PLL synchronizes a signal (usually a local oscillator output) with a reference or an input signal in frequency as well as in phase.
Phase locking is a useful technique that can provide effective synchronization solutions in many data transmission systems such as optical communications, telecommunications, disk drive systems, and local networks, in which data is transmitted in baseband or passband. In general, only data signals are
transmitted in most of these applications; namely, clock signals are not transmitted in order to save hardware cost. Therefore, the receiver should have some schemes to extract the clock information from
the received data stream in order to recover transmitted data. The scheme is called a timing recovery or clock recovery circuit.
【目　录】:
57.1 Introduction
57.2 PLL Techniques
57.3 Building Blocks of the PLL Circuit