Cadence自动布线器SE的tutorial

Helgain

【文件名】:06515@52RD_slc_tutorial.rar
【格　式】:rar
【大　小】:48K
【简　介】:This tutorial will enable a new user of Silicon Ensemble to step through the System Level Constraint (SLC) flow. It should take 2-4 hours to step through the tutorial the first time. Included in this bundle, are all the necessary files and instructions to read in design data and constraints,
then complete place and route using the Silicon Ensemble SLC set of tools.
【目　录】:
1. Loading in the initial design data (library information, Verilog netlist, and synthesis constraints)
2. Initial die size estimation and automatic floorplan creation
3. I/O placement
4. Automatic timing driven placement of block macros
5. Initial power routing (final power routing is done later in the tutorial)
6. Timing driven placement and concurrent placement based optimization through gate resizing and
buffer insertion/deletion for the standard cells
7. Clock tree synthesis and placement
8. Routing the design (final power routing, clock routing, signal routing)
9. Extracting parasitics using HyperExtract
10. Post clock tree path optimization through gate resizing and buffer insertion using parasitics from
HyperExtract
11. Incremental final routing to repair optimized nets
12. Post Routing Timing Analysis
13. Output of final Verilog, DEF, SDF, and GDSII
14. Other useful menus/commands/thoughts