可综合的Verilog语法

Kittyeen

【文件名】:0658@52RD_可综合的Verilog语法（剑桥大学，影印）.rar
【格　式】:rar
【大　小】:299K
【简　介】:Synthesizable Verilog is a subset of the full Verilog HDL [9] that lies within the domain of current synthesis tools (both RTL and behavioral).
This document specifies a subset of Verilog called V0.1 This subset is intended as a vehicle for the rapid prototyping of ideas.
The method chosen for developing a semantics of all of synthesizable Verilog
is to start with something too simple { V0 { and then only to make it more
complicated when the simple semantics breaks. This way it is hoped to avoid
unnecessary complexity. It is planned to dene sequence of bigger and bigger subsets (V1, V2 etc.) that will converge to the version of Verilog used in the VFE project2 at Cambridge.
【目　录】:
1 Syntax
2 Semantic Pseudo-Code
3 Event Semantics
4 Trace Semantics
5 Cycle Semantics

lvlin

<P>先看看</P>