DSI_Specification_v01-01-00_r11

freedom2008

DSI接口的规范文档，作为LCD 显示接口，MIPI定义了DBI、DPI、DSI接口，DSI接口被多家平台上支持，
并得到了广泛的推广使用，该文档即时DSI的规范
【文件名】:12914@52RD_DSI_Specification_v01-01-00_r11.pdf
【格　式】:pdf
【大　小】:1249K
【简　介】:

【目　录】:
Contents
38 Draft Version 1.01.00 Release 11 – 21 February 2008 .................................................................................... i
39 1 Overview .............................................................................................................................................. 11
40 1.1 Scope ............................................................................................................................................ 11
41 1.2 Purpose ......................................................................................................................................... 11
42 2 Terminology (informative) .................................................................................................................... 12
43 2.1 Definitions .................................................................................................................................... 12
44 2.2 Abbreviations ............................................................................................................................... 13
45 2.3 Acronyms ..................................................................................................................................... 13
46 3 References (informative) ....................................................................................................................... 16
47 3.1 Display Bus Interface Standards for Parallel Signaling (DBI and DBI-2) .................................... 16
48 3.2 Display Pixel Interface Standards for Parallel Signaling (DPI and DPI-2) ................................... 16
49 3.3 MIPI Alliance Standard for Display Command Set (DCS) ........................................................... 17
50 3.4 MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) ..................................................... 17
51 3.5 MIPI Alliance Specification for D-PHY (D-PHY) ........................................................................ 17
52 4 DSI Introduction ................................................................................................................................... 18
53 4.1 DSI Layer Definitions ................................................................................................................... 19
54 4.2 Command and Video Modes ......................................................................................................... 20
55 4.2.1 Command Mode .................................................................................................................... 20
56 4.2.2 Video Mode Operation .......................................................................................................... 20
57 4.2.3 Virtual Channel Capability .................................................................................................... 21
58 5 DSI Physical Layer ............................................................................................................................... 22
59 5.1 Data Flow Control ......................................................................................................................... 22
60 5.2 Bidirectionality and Low Power Signaling Policy ......................................................................... 22
61 5.3 Command Mode Interfaces ........................................................................................................... 23
62 5.4 Video Mode Interfaces .................................................................................................................. 23
63 5.5 Bidirectional Control Mechanism .................................................................................................. 23
5.6 Clock Management ........................................................................................................................ 64 .......... 24
65 5.6.1 Clock Requirements .............................................................................................................. 24
66 5.6.2 Clock Power and Timing ....................................................................................................... 25
67 5.7 System Power-Up and Initialization .............................................................................................. 25
68 6 Multi-Lane Distribution and Merging ................................................................................................... 27
69 6.1 Multi-Lane Interoperability and Lane-number Mismatch ............................................................. 28
70 6.1.1 Clock Considerations with Multi-Lane .................................................................................. 29
71 6.1.2 Bi-directionality and Multi-Lane Capability ......................................................................... 29
72 6.1.3 SoT and EoT in Multi-Lane Configurations .......................................................................... 29
73 7 Low-Level Protocol Errors and Contention ........................................................................................... 32
74 7.1 Low-Level Protocol Errors ............................................................................................................ 32
75 7.1.1 SoT Error ............................................................................................................................... 32
76 7.1.2 SoT Sync Error ...................................................................................................................... 33
77 7.1.3 EoT Sync Error ...................................................................................................................... 33
78 7.1.4 Escape Mode Entry Command Error ..................................................................................... 34
79 7.1.5 LP Transmission Sync Error .................................................................................................. 34
80 7.1.6 False Control Error ................................................................................................................ 34
81 7.2 Contention Detection and Recovery .............................................................................................. 35
82 7.2.1 Contention Detection in LP Mode ......................................................................................... 35
83 7.2.2 Contention Recovery Using Timers ...................................................................................... 35
84 7.3 Additional Timers .......................................................................................................................... 38
85 7.3.1 Turnaround Acknowledge Timeout (TA_TO) ....................................................................... 38
86 7.3.2 Peripheral Reset Timeout (PR_TO) ....................................................................................... 38
87 7.4 Acknowledge and Error Reporting Mechanism ............................................................................ 39
88 8 DSI Protocol ......................................................................................................................................... 40
89 8.1 Multiple Packets per Transmission ................................................................................................ 40
90 8.2 Packet Composition ....................................................................................................................... 41
91 8.3 Endian Policy ................................................................................................................................ 42
8.4 General Packet Structure ............................................................................................................... 92 ......... 42
93 8.4.1 Long Packet Format ............................................................................................................... 42
94 8.4.2 Short Packet Format .............................................................................................................. 44
95 8.5 Common Packet Elements ............................................................................................................. 44
96 8.5.1 Data Identifier Byte ............................................................................................................... 44
97 8.5.2 Error Correction Code ........................................................................................................... 45
98 8.6 Interleaved Data Streams ............................................................................................................... 45
99 8.6.1 Interleaved Data Streams and Bi-directionality ..................................................................... 46
100 8.7 Processor to Peripheral Direction (Processor-Sourced) Packet Data Types .................................. 46
101 8.8 Processor-to-Peripheral Transactions – Detailed Format Description ........................................... 47
102 8.8.1 Sync Event (H Start, H End, V Start, V End), Data Type = xx 0001 (x1h) ........................... 47
103 8.8.2 EoTp, Data Type = 00 1000 (08h) ......................................................................................... 48
104 8.8.3 Color Mode Off Command, Data Type = 00 0010 (02h) ...................................................... 49
105 8.8.4 Color Mode On Command, Data Type = 01 0010 (12h) ....................................................... 49
106 8.8.5 Shutdown Peripheral Command, Data Type = 10 0010 (22h) ............................................... 49
107 8.8.6 Turn On Peripheral Command, Data Type = 11 0010 (32h) ................................................. 49
108 8.8.7 Generic Short WRITE Packet with 0, 1, or 2 parameters, Data Types = 00 0011 (03h), 01
109 0011 (13h), 10 0011 (23h), Respectively .............................................................................................. 49
110 8.8.8 Generic READ Request with 0, 1, or 2 Parameters, Data Types = 00 0100 (04h), 01 0100
111 (14h), 10 0100(24h), Respectively ........................................................................................................ 49
112 8.8.9 DCS Commands .................................................................................................................... 50
113 8.8.10 Set Maximum Return Packet Size, Data Type = 11 0111 (37h) ............................................ 51
114 8.8.11 Null Packet (Long), Data Type = 00 1001 (09h) ................................................................... 51
115 8.8.12 Blanking Packet (Long), Data Type = 01 1001 (19h)............................................................ 51
116 8.8.13 Generic Long Write, Data Type = 10 1001 (29h) .................................................................. 51
117 8.8.14 Packed Pixel Stream, 16-bit Format, Long packet, Data Type 00 1110 (0Eh) ...................... 52
118 8.8.15 Packed Pixel Stream, 18-bit Format, Long packet, Data type = 01 1110 (1Eh) .................... 53
119 8.8.16 Pixel Stream, 18-bit Format in Three Bytes, Long packet, Data Type = 10 1110 (2Eh) ....... 54
120 8.8.17 Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh) ................... 55
8.8.18 DO NOT USE and Reserved Data Types .............................................................................. 121 55
122 8.9 Peripheral-to-Processor (Reverse Direction) LP Transmissions ................................................... 56
123 8.9.1 Packet Structure for Peripheral-to-Processor LP Transmissions ........................................... 56
124 8.9.2 System Requirements for ECC and Checksum and Packet Format ....................................... 57
125 8.9.3 Appropriate Responses to Commands and ACK Requests.................................................... 57
126 8.9.4 Format of Acknowledge and Error Report and Read Response Data Types ......................... 58
127 8.9.5 Error Reporting Format ......................................................................................................... 59
128 8.10 Peripheral-to-Processor Transactions – Detailed Format Description ........................................... 60
129 8.10.1 Acknowledge and Error Report, Data Type 00 0010 (02h) ................................................... 61
130 8.10.2 Generic Short Read Response, 1 or 2 Bytes, Data Types = 01 0001 or 01 0010, Respectively61
131 8.10.3 Generic Long Read Response with Optional Checksum, Data Type = 01 1010 (1Ah) ......... 62
132 8.10.4 DCS Long Read Response with Optional Checksum, Data Type 01 1100 (1Ch) ................. 62
133 8.10.5 DCS Short Read Response, 1 or 2 Bytes, Data Types = 10 0001 or 10 0010, Respectively . 62
134 8.10.6 Multiple Transmissions and Error Reporting ........................................................................ 62
135 8.10.7 Clearing Error Bits ................................................................................................................. 63
136 8.11 Video Mode Interface Timing ....................................................................................................... 63
137 8.11.1 Transmission Packet Sequences ............................................................................................ 63
138 8.11.2 Non-Burst Mode with Sync Pulses ........................................................................................ 64
139 8.11.3 Non-Burst Mode with Sync Events ....................................................................................... 65
140 8.11.4 Burst Mode ............................................................................................................................ 66
141 8.11.5 Parameters ............................................................................................................................. 67
142 8.12 TE Signaling in DSI ...................................................................................................................... 68
143 9 Error-Correcting Code (ECC) and Checksum ....................................................................................... 70
144 9.1 Packet Header Error Detection/Correction .................................................................................... 70
145 9.2 Hamming Code Theory ................................................................................................................. 70
146 9.3 Hamming-modified Code Applied to DSI Packet Headers ........................................................... 70
147 9.4 ECC Generation on the Transmitter .............................................................................................. 74
148 9.5 Applying ECC on the Receiver ..................................................................................................... 75
9.6 Checksum Generation for Long Packet Payloads 149 .......................................................................... 75
150 10 Compliance, Interoperability, and Optional Capabilities................................................................... 77
151 10.1 Display Resolutions ....................................................................................................................... 77
152 10.2 Pixel Formats ................................................................................................................................ 78
153 10.2.1 Video Mode ........................................................................................................................... 78
154 10.2.2 Command Mode .................................................................................................................... 78
155 10.3 Number of Lanes ........................................................................................................................... 78
156 10.4 Maximum Lane Frequency ............................................................................................................ 78
157 10.5 Bidirectional Communication ........................................................................................................ 79
158 10.6 ECC and Checksum Capabilities ................................................................................................... 79
159 10.7 Display Architecture ...................................................................................................................... 79
160 10.8 Multiple Peripheral Support .......................................................................................................... 79
161 10.9 EoTp Support and Interoperability ................................................................................................ 79
162 Annex A Contention Detection and Recovery Mechanisms (informative) ................................................... 80
163 A.1 PHY Detected Contention ............................................................................................................. 80
164 A.1.1 Protocol Response to PHY Detected Faults ........................................................................... 80
165 Annex B Checksum Generation Example (informative) ............................................................................... 86
166
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