Logic Synthesis 中面积优化技巧介绍

Donna

【文件名】:06430@52RD_Logic Synthesis 中面积优化技巧介绍(2).rar
【格　式】:rar
【大　小】:40K
【简　介】:With increasing clock frequencies and design complexities, as well as tighter time to market demands, area optimization can become the odd man out in ASIC design. It’s the old “good, fast, cheap - pick any two”, where “good” represents timing/design closure, “fast” represents time to market, and “cheap” represents area and power optimization. With time to market as astake in the ground, area optimization and timing closure become perceived as mutually exclusive goals. A striking example of this perception occurred to me at SNUG San Jose 2000 in a Synopsys tutorial titled “Getting the Most from Design Compiler for Area & Delay”. The tutorial was presented in two distinct sections, one for area and one for timing.
【目　录】:
1.0 Introduction
2.0 Why Size Matters
3.0 Addressing The Concerns
4.0 Key Methodology Issues
5.0 MIN/MAX Methodology Revisited
6.0 Nitty Gritty Dirt Details
7.0 Conclusions and Future Work
8.0 References