XILINX ZYNQ资料

summerwinds

xilinx 最新EPP资料（FPGA+双核ARM)


【文件名】:12531@52RD_ds187_XC7Z010_XC7Z020_Data_Sheet.pdf
【格　式】:pdf
【大　小】:1039K
【简　介】:
【目　录】:




Zynq-7000 Extensible Processing Platform (EPP)—First Generation EPP Architecture
Processing System (PS)
Dual-core ARM® Cortex™-A9 based application processor unit (APU)
• 2.5 DMIPS/MHz
• CPU frequency: up to 800 MHz
• Coherent multiprocessor support
• ARMv7-A architecture
• TrustZone® security
• Thumb®-2 instruction set
• Jazelle® RCT execution Environment Architecture
• NEON™ media-processing engine
• Single and double precision Vector Floating Point Unit (VFPU)
• Coresight™ and Program Trace Macrocell (PTM) supports
non-intrusive debug
• Timer and Interrupts
• Three watchdog timers
• One global timer
• Two triple-timer counters
Caches
• 32 KB Level 1 4-way set-associative instruction and data caches
(independent for each core)
• 512 KB 8-way set-associative Level 2 cache
(shared between the cores)
• Byte-parity support
On-chip memory
• On-chip boot ROM
• 256 KB on-chip RAM (OCM)
• Byte-parity support
External memory interfaces
• Multiprotocol dynamic memory controller
• 16-bit or 32-bit interfaces to DDR2, DDR3, or LPDDR2
memories
• ECC support in 16-bit mode
• 1 GB of address space using single rank of 16- or 32-bit wide
memories
• Static memory interfaces
• 8-bit SRAM data bus with up to 128 MB support
• Parallel NOR flash support
• ONFI1.0 NAND flash support
- 1-bit ECC
• 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or dual Quad-SPI
(4- or 8-bit) serial NOR flash
8-channel DMA controller
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory,
and scatter-gather transaction support
• Fully user programmable through microcode
• Peripheral flow control
• Trustzone security support
I/O peripherals and interfaces
• Two 10/100/1000 tri-speed Ethernet MAC peripherals with
IEEE 802.3 and IEEE 1588 revision 2.0 support
• Scatter-gather DMA capability
• Recognition of 1588 rev. 2 PTP frames
• GMII and RGMII interface
• Two USB 2.0 OTG peripherals each supporting up to 12 Endpoints
• USB 2.0 compliant device IP core
• Supports on-the-go, high-speed, full-speed, and low-speed
modes
• Intel™ EHCI compliant USB host
• 8-bit ULPI external PHY interface
• Two full CAN 2.0B compliant CAN bus interfaces
• CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard
compliant
• External PHY interface
• Two SD/SDIO 2.0/MMC3.31 compliant controllers
• Two full-duplex SPI ports with three peripheral chip selects and
master and slave support
• Two high-speed UARTs (up to 1 Mb/s)
• Two master and slave I2C interfaces
• 118 independent general-purpose I/O (GPIOs)
• Flexible multiplexed I/O (MIO) for peripheral pin assignments
Interconnect
• High bandwidth AXI connectivity within PS and between PS and PL
• AMBA® protocol based
• QoS support on critical masters for latency and bandwidth control
Programmable Logic (PL)
Configurable logic blocks (CLB)
• Lookup tables (LUT)
• Flip-flops
• Cascadeable adders
36 Kb block RAM, true dual-port
• Up to 72-bits wide
• Configurable as dual 18 Kb