Writing Efficient Testbenches（适合初学者）

Camilla

【文件名】:06426@52RD_how to write testbench（适合初学者）.rar
【格　式】:rar
【大　小】:196K
【简　介】:Due to increases in design size and complexity, digital design verification has become an increasingly difficult and laborious task. To meet this challenge, verification engineers rely on several verification tools and methods. For large, multi-million gate designs, engineers typically use a suite of formal verification tools. However, for smaller designs, design engineers usually find that HDL simulators with testbenches work best.
【目　录】:无目录

msmei

既然是Xilinx的Application Note，就应该提前注明。这篇paper是针对FPGA的，对ASIC Verification的指导意义不大。