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ESD好書分享, 適合初學者!
【文件名】:111017@52RD_ESD in Silicon Integrated Circuits.rar
【格 式】:rar
【大 小】:3407K
【简 介】:
【目 录】:
1 Introduction
1.1 Background
1.2 The ESD Problem
1.3 Protecting Against ESD
1.4 Outline of the Book
2 ESD Phenomenon
2.1 Introduction
2.2 Electrostatic Voltage
2.3 Discharge
2.4 ESD Stress Models
3 Test Methods
3.1 Introduction
3.2 Human Body Model (HBM)
3.3 Machine Model (MM)
3.4 Charged Device Model (CDM)
3.5 Socket Device Model (SDM)
3.6 Metrology, Calibration, Verification
3.7 Transmission Line Pulsing (TLP)
3.8 Failure Criteria
3.9 Summary
4 Physics and Operation of ESD Protection Circuit Elements
4.1 Introduction
4.2 Resistors
4.3 Diodes
4.4 Transistor Operation
4.5 Transistor Operation under ESD Conditions
4.6 Electrothermal Effects
4.7 SCR Operation
4.8 Conclusion
5 ESD Protection Circuit Design Concepts and Strategy
5.1 The Qualities of Good ESD Protection
5.2 ESD Protection Design Methods
5.3 Selecting an ESD Strategy
5.4 Summary
6 Design and Layout Requirements
6.1 Introduction
6.2 Thick Field Device
6.3 nMOS Transistors (FPDs)
6.4 Gate-Coupled nMOS (GCNMOS)
6.5 Gate Driven nMOS (GDNMOS)
6.6 SCR Protection Device
6.7 ESD Protection Design Synthesis
6.8 Total Input Protection
6.9 ESD Protection Using Diode-Based Devices
6.10 Power Supply Clamps
6.11 Bipolar and BiCMOS Protection Circuits
6.12 Summary
7 Advanced Protection Design
7.1 Introduction
7.2 PNP-Driven nMOS (PDNMOS)
7.3 Substrate Triggered nMOS (STNMOS)
7.4 nMOS Triggered nMOS (NTNMOS)
7.5 ESD for Mixed-Voltage I/O
7.6 CDM Protection
7.7 SOI Technology
7.8 High-Voltage Transistors
7.9 BiCMOS Protection
7.10 RF Designs
7.11 General I/O Protection Schemes
7.12 Design/Layout Errors
7.13 Summary
8 Failure Modes, Reliability Issues, and Case Studies
8.1 Introduction
8.2 Failure Mode Analysis
8.3 Reliability and Performance Considerations
8.4 Advanced CMOS Input Protection
8.5 Optimizing the Input Protection Scheme
8.6 Designs for Special Applications
8.7 Process Effects on Input Protection Design
8.8 Total IC Chip Protection
8.9 Power Bus Protection
8.10 Internal Chip ESD Damage
8.11 Stress Dependent ESD Behavior
8.12 Failure Mode Case Studies
8.13 Summary
9 Influence of Processing on ESD
9.1 Introduction
9.2 High Current Behavior
9.3 Cross Section of a MOS Transistor
9.4 Drain-Source Implant Effects
9.5 p-Well Effects
9.6 n-Well Effects
9.7 Epitaxial Layers and Substrates
9.8 Gate Oxides
9.9 Silicides
9.10 Contacts
9.11 Interconnect and Metalization
9.12 Gate Length Dependencies
9.13 Silicon-on-Insulator (SOI)
9.14 Bipolar Transistors
9.15 Diodes
9.16 Resistors
9.17 Reliability Trade-Offs
9.18 Summary
10 Device Modeling of High Current Effects
10.1 Introduction
10.2 The Physics of ESD Damage
10.3 Thermal (“Second”) Breakdown
10.4 Analytical Models Using the Heat Equation
10.5 Electrothermal Device Simulations
10.6 Conclusion
11 Circuit Simulation Basics, Approaches, and Applications
11.1 Introduction
11.2 Modeling the MOSFET
11.3 Modeling Bipolar Junction Transistors
11.4 Modeling Diffusion Resistors
11.5 Modeling Protection Diodes
11.6 Simulation of Protection Circuits
11.7 Electrothermal Circuit Simulations
11.8 Conclusion
12 Conclusion
12.1 Long-Term Relevance of ESD In ICs
12.2 State-of-the-Art for ESD Protection
12.3 Current Limitations
12.4 Future Issues
Index
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发表于 2011-10-17 15:17:19
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