Mentor的关于状态机设计的文章

fredericada

【文件名】:06418@52RD_smdesign.rar
【格　式】:rar
【大　小】:89K
【简　介】:The design of finite state machines is a key application of the HDL Designer Series™ tools. Just as it is possible for a designer to write VHDL that results in poorly performing state machines, it is possible to use HDL Designer Series™ tools to generate VHDL that results in poorly performing state machines. A key component for the successful application of a HDL design tool is the users’ confidence that the tool can be used to generate
predictable, high-performance, finite state machine, HDL code.
This applications note explains how elements of the HDL Designer Series™ state diagram editor greatly impact the resulting HDL code.
The examples in this applications note apply to VHDL. The concepts are equally applicable to designing with the Verilog™ hardware description language.
【目　录】:无目录