找回密码
 注册
搜索
查看: 716|回复: 0

[FPGA资料] 可综合的Verilog语法

[复制链接]
发表于 2006-4-18 10:54:00 | 显示全部楼层 |阅读模式
【文件名】:06418@52RD_Verilog-Semantics.rar
【格 式】:rar
【大 小】:299K
【简 介】:Synthesizable Verilog is a subset of the full Verilog HDL [9] that lies within the domain of current synthesis tools (both RTL and behavioral).
This document speci es a subset of Verilog called V0.1 This subset is intended as a vehicle for the rapid prototyping of ideas.
The method chosen for developing a semantics of all of synthesizable Verilog
is to start with something too simple { V0 { and then only to make it more
complicated when the simple semantics breaks. This way it is hoped to avoid
unnecessary complexity. It is planned to de ne sequence of bigger and bigger subsets (V1, V2 etc.) that will converge to the version of Verilog used in the VFE project2 at Cambridge.
【目 录】:
1 Syntax
2 Semantic Pseudo-Code
3 Event Semantics
4 Trace Semantics
5 Cycle Semantics


本帖子中包含更多资源

您需要 登录 才可以下载或查看,没有账号?注册

×
高级模式
B Color Image Link Quote Code Smilies

本版积分规则

Archiver|手机版|小黑屋|52RD我爱研发网 ( 沪ICP备2022007804号-2 )

GMT+8, 2024-11-23 12:24 , Processed in 0.050455 second(s), 17 queries , Gzip On.

Powered by Discuz! X3.5

© 2001-2023 Discuz! Team.

快速回复 返回顶部 返回列表