verilog and VHDL编写的比较与学习-good

daneylulu

【文件名】:06411@52RD_verilog and VHDL.rar
【格　式】:rar
【大　小】:371K
【简　介】:VHDL and Verilog
®
HDL are high level description languages for
system and circuit design. These languages support various abstraction
levels of design, including architecture-specific design. At the higher
levels, these languages can be used for system design without regard
to a specific technology. To create a functional design, you only need
to consider a specific target technology. However, to achieve optimal
performance and area from your target device, you must become
familiar with the architecture of the device and then code your design
for that architecture.
Efficient, standard HDL code is essential for creating good designs. The
structure of the design is a direct result of the structure of the HDL
code. Additionally, standard HDL code allows designs to be reused in
other designs or by other HDL designers.
This document provides the preferred coding styles for the Actel
architecture. The information is to be used as reference material with
instructions to optimize your HDL code for the Actel architecture.
Examples in both VHDL and Verilog code are provided to illustrate
these coding styles and to help implement the code into your design.
【目　录】:
1 Design Flow
2 Technology Independent Coding Styles
3 Performance Driven Coding
4 Technology Specific Coding Techniques