(FPGA) Quartus II : Timing Closure Floorplan

yongqin2005

How to make the use of Quartus II to optimize design , inprove the speed,
and reduce area in FPGA , through methods  such as Timing Closure Floorplan,
Chip Editor, and so on.
IF u have some reference , please send  email to : yongqin2005@126.com
for your help, Thank u very much

dawn

<P>楼主是中国人还是外国人啊</P><P>英文不好</P><P>看不懂</P>

lcz209

<P>写中文好不好 英文这么好就去问外国人 OK</P>[em10]

blueprince

看得懂 但是回答不了你的问题

thisman

<P>提高速度降低面积是矛盾的,根据实际情况来取舍.一般可以通过模块分割,logiclock 之类的方法来提高局部的timing,或许可以减少用于提高速度带来的面积增加过多.</P>[br]<p align=right><font color=red>+3 RD币</font></p>

blueprince

<P>在 EDA技术与VHDL 一书中，</P><P>有专门的讲解优化的</P>