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公司介绍：
三星(Samsung)半导体是排名仅次于英特尔的全球第2大半导体芯片厂商, 2010年销售额超过280亿美金。 它的Memory 产品一直排名第1, 这几年它在System LSI领域发展也很快, 比如在AP SoC(应用处理器)处于世界领先地位, 广泛用在智能手机, 平板电脑(Tablet), E-book等移动设备中。
三星半导体杭州研究所的主要业务是超大规模集成电路设计, 底层软硬件开发及系统解决方案的提供.
立足中国，面向世界，三星半导体杭州研究所的目标是成为韩国三星半导体在海外最重要的，技术一流的研发中心，为中国市场提供有竞争力的半导体产品和Total Solution。
目前主要的部门是AP(应用处理器）， MCU(微控制器）和Analog IP 的芯片设计，软件开发和系统解决方案提供。
我们现招聘优秀毕业生和有经验的工程师， 重点做AP(应用处理器) SoC芯片产品开发，欢迎富有激情、敢于梦想的你和Samsung一起快速成长！
公司地址：杭州市滨江区江南大道380号威陵大厦9-13层
请有意者将详细中英文简历发往ssc.sscr@samsung.com
职位说明：
一、Senior and Junior Android/Linux Platform Test Engineer/ Senior and Junior Hardware Test Engineer
Organization introduction:
Solution Team is a business unit under Samsung Semiconductor China R&D. Solution Team focus on the Platform Design based on Samsung Application Processor. Solution Team‘s product covers Smart phone, Tablet, E-book, PND etc. Solution Team’s customers spread all over the world, and many of them are key players in relevant industry in the world.
Test Part of Solution Team will support Android Platform, Linux Platform test on various hardware platforms.
1. Senior/Junior Android/Linux Platform Test Engineer
Scope of Responsibilities:
- Take leadership in Android/ Linux platform test project. Plan test activities.
- Create Linux platform test plan, test specifications and test cases, based on Android/Linux.
- Create test applications or tools to test Android /Linux BSP drivers, Framework and application.
- Define test process and methodology to make sure the quality of Android/Linux platform releases.
- Execute test on different releases and report issues accurately
- Effectively analyze issues cause among different SW layers, HW, Configuration.
Specific Knowledge/Skills:
- BS/MS degree with software development or software testing experience;
- One of development languages such C, C++ , Shell Script or Java required;
- Experience on Project Management are a plus;
- Experience with Linux BSP DEV desired;
- Good English verbal and written communication skills;
- Passion to work as a professional software testing engineer, with initiative, innovative spirit;
- Good understanding to test methodology, test cycle, process is a plus.
2. Senior/Junior Hardware Test Engineer
Scope of Responsibilities:
- Take leadership in hardware platform test. Plan test activities.
- Create hardware platform test plan, test specifications and test cases, based on ARM11/Cortex-A8/Cortex-A9 etc.
- Create Auto Test Hardware Platform
- Support to build hardware platform.
- Define test process and methodology to make sure the quality of Hardware platform releases.
- Execute test on different releases and report issues accurately
- Effectively analyze issues cause among different Application , peripheral.
Specific Knowledge/Skills:
- BS/MS degree with Hardware development or Hardware testing experience;
- 1+ years experience in Schematic /PCB design.
- Experience on Project Management are a plus;
- Experience with Mobile Device Hardware Develop and Firmware Debugging desired;
- Good English verbal and written communication skills;
- Passion to work as a professional software testing engineer, with initiative, innovative spirit;
- Good understanding to test methodology, test cycle, process is a plus.
二、AP SoC Design Engineer/ AP FPGA and Validation Engineer
Application Prosessor(AP,应用处理器) is very complex SoC(System-on-Chip) based on ARM-core with the application in the moble device market, such as Smart Phones, Portable Media Player, GPS Navigator, E-Book, MID, Tablet and so on.
The ARM core can be ARM9, ARM11, Cortex A8/A9 and IPs we design and integrate are image/video co-processor, graphics core, controller for SDRAM/DDR, USB, HDMI, Memory Card and different kinds of peripherals, like Audio I2S interface, SPI, UART, I2C, just to name a few.
1. AP SoC Design Engineer
Scope of Responsibility:
Be responsible for all aspect of design activities in the complex AP SoC design.
This includes but not limited to the following tasks:
- Design specification, micro-architecture definition and IP creation.
- Logic design and implementation by high-level languages(such as Verilog) at both the IP/block level and SoC level.
- IP/chip level verification : specialized and intensive verification of IP and SoC design using modern verification languages and flows.
- Synthethis, DFT, STA and participation in the final timing and SI closure.
- Work closely with marketing, SW and solution team in definition, development and support for competitive SoC products for the China market.
Requirement:
* BS, MS or Ph.D degree on the major of Electronics, Computer Science, Microelectronics and related.
* Experience on digital design and simulation/verification based on high-level languages(Verilog, VHDL, C/C++).
* Familiar with UNIX/Linux system and simulation tools from main EDA vendors.
* Basic concept of ASIC/SoC design flow from the spec to tapeout.
* Basic knowledge of ARM processor and AMBA bus architecture is preferred.
* Experience/knowledge on Multimedia(eg. video compression and display) or External Memory Interfaces(eg. DDR, Memory Card) will be a big plus.
* Experience on complex HW/SW system development based on CPU and/or FPGA will be a big plus.
* Ability in quick learning and working effectively both in the team and self-independent mode.
2. AP FPGA and Validation Engineer
Scope of responsibilities:
* Develop pre-silicon verification plan, create C test patterns and perform FPGA verification for SoC design before tapeout.
* Develop silicon validation plan, create C test cases and applications, and perform silicon validation.and electrical characteristics tests for SoC chips.
* Work closely with the PE/TE for product pattern development and support mass production of silicon products.
* Define FPGA prototyping H/W system and silicon EVA board, support the HW team on board design and bring-up of H/W board.
* For senior position, he/she will also be responsible for porting SoC design into FPGA including doing partition into multiple FPGAs for large SoC design, perform FPGA implementation, i.e. RTL coding/change, simulation, synthesis, P&R and config bitstream generation.
* For very senior position, he will be responsible for mapping SoC design into HW emulation system, like Palladium, compile and run through the test cases to bring-up the complex palladium platform.
* The verification/validation can be done on module-level, scenario and some performance tests, so a good understanding of module/IP, chip and the whole SoC system is required, he/she will work closely with the design team, HW team and SW team and act as the main interface for talk between those functional teams.
Requirements:
* BS, MS and Ph.D degree in electrical engineering or related majors.
* Good HW test and validation experience on the complex embedded system based on MCU/DSP/MPU and/or FPGA.
* Good knowledge of MCU/DSP architecture and experiences in C/ASM programming and debug.
Experience with ARM-based SoC programming and debug tools will be a plus.
* Proficiency in using lab equipments & tools, eg. Logic Analyzer, Oscilloscope, measurement equipments and debugging tools.
* Strong debugging and problem solving skills with the ability in quick learning and independent work.
* For board designer, hands on experience in component selection, schematics and PCB design is required,
experience on the high speed design, signal integrity will a plus.
* For FPGA designer, good experience on FPGA prototyping development based on Xilinx or Altera is required,
this means he/she has hands-on-experience in Verilog/VHDL design, simulation and FPGA implementation.
Experience on doing FPGA partition for large ASIC/SoC design and achieving high frequency performance for complex and large design will be a plus.
* Knowledge of SoC design & verification methodology will be a plus
* Knowledge or experience in complex HW/SW system development based on CPU/FPGA will be a big plus, eg. multimedia or wireless communication application.
* Knowledge or experience in Palladium emulation system will be a big plus.
* Ability in quick learning and working effectively both in the team and self-independent mode. |
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IP卡
狗仔卡
发表于 2011-2-8 17:26:12
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