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【文件名】:06329@52RD_状态机设计经典论文 .rar
【格 式】:rar
【大 小】:113K
【简 介】:Abstract†: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler1.Verilog and VHDL coding styles will be presented. Different methodologies will be compared using real-world examples.
【目 录】:
1.0 Introduction
2.0 Basic HDL coding
3.0 State assignment
4.0 Coding state transitions
5.0 Outputs
6.0 Inputs
7.0 FSM extract
8.0 Timing constraints
9.0 Synthesis strategies
10.0 Compile results
11.0 Hints, tips, tricks, mysteries
12.0 Acknowledgments
13.0 References
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发表于 2006-3-29 18:18:00
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