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[IC设计资料] Verification Methodology Manual for SystemVerilog

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发表于 2010-6-12 15:11:57 | 显示全部楼层 |阅读模式
【文件名】:10612@52RD_Verification Methodology Manual for SystemVerilog.rar
【格 式】:rar
【大 小】:2598K
【简 介】:
【目 录】:




Verification MethodologyManualforSystemVerilog
by
Janick Bergeron
Eduard Cerny
Alan Hunter
Andrew Nightingale

CHAPTER 1Introduction
CHAPTER 2Verification Planning
CHAPTER 3Assertions
高级模式
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