【文件名】:06324@52RD_几个constraint约束教程，非常不错(1).rar
【格 式】:rar
【大 小】:124K
【简 介】:What effects do timing constraints have on your project?
• The implementation tools do not attempt to find the place & route that will
obtain the best speed
– Instead, the implementation tools try to meet your performance
expectations
• Performance expectations are communicated with timing constraints
– Timing constraints improve the design performance by placing logic closer
together so shorter routing resources can be used
– Note that when we discuss using the Constraints Editor, we are referring to
the Xilinx Constraints Editor
【目 录】:
1.Introduction
2.Global Constraints
3.The Constraints Editor
4.Summary
【文件名】:06324@52RD_几个constraint约束教程，非常不错(2).rar
【格 式】:rar
【大 小】:190K
【简 介】:• Using global timing constraints (PERIOD, OFFSET, and PAD-TO-PAD) will
constrain your entire design
• Using only global constraints often leads to over-constrained designs
– Constraints are too tight
– Increases compile time and can prevent timing objectives from being met
– Review performance estimates provided by your synthesis tool or the Post-
Map Static Timing Report
• Path-specific constraints override the global constraints on specified paths
– This allows you to loosen the timing requirements on specific paths
【目 录】:
• Introduction
• Creating Groups
• OFFSET Constraints
• Summary
【文件名】:06324@52RD_003path_constraints.rar
【格 式】:rar
【大 小】:112K
【简 介】:• The PERIOD constraint automatically accounts for two-phase clocks
– Includes adjustments for non-50-percent duty-cycle clocks
• Example: A PERIOD constraint of 10 ns on CLK will apply a 5-ns constraint
between these two flip-flops
• No path-specific constraints are required for this case
【目 录】:
• Inter-Clock Domain Constraints
• Multi-cycle Paths
• False Paths
• Miscellaneous Constraints
• Summary
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发表于 2006-3-24 12:32:00
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