ALLEGRO导入网表出错

jicks

原理图是用ORCAD CIS 画的，而且导出网表时没有问题。
可在PCB EDIT中导入网表时出现以下错误：
好像是说没有找到文件，可在网表文件侠中有几个DAT文件的呀。
谢谢！！

Cadence Design Systems, Inc. netrev 16.2 Mon Jul 20 22:12:23 2009
(C) Copyright 2002 Cadence Design Systems, Inc.

------ Directives ------

RIPUP_ETCH FALSE;
RIPUP_SYMBOLS NEVER;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'D:/cadence/works/test';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'D:/cadence/works/test/test.brd';
NEW_BOARD_NAME 'D:/cadence/works/test/test.brd';

CmdLine: netrev -$ -i D:/cadence/works/test -y 3 D:/cadence/works/test/#Taaaaaa07152.tmp

------ Preparing to read pst files ------


#1   ERROR(24) File not found
     Packager files not found

#2   ERROR(102) Run stopped because errors were detected

netrev run on Jul 20 22:12:23 2009

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

  2 errors detected
No oversight detected
No warning detected

cpu time      0:00:37
elapsed time  0:00:00

jicks

顶起呀。。。。。。。。。。。