國家晶片系統設計中心最新的Logic Synthesis教材

dominicyao

【文件名】:06228@52RD_國家晶片系統設計中心最新的Logic Synthesis教材.pdf
【格　式】:pdf
【大　小】:3284K
【简　介】:
【目　录】:



Schedule
Introduction to Logic Synthesis
  Introduction
  Design object
  Static Timing Analysis (STA)
  Synopsys design analyzer environment
HDL Coding For Synthesis
  Synthesizable Verilog HDL
  Some tricks in Verilog HDL
  Designware library
Lab Time (Lab1)
Synthesis Training Course
Schedule(day
Design Constraint
  Setting design environment
  Setting design constraint
Design Optimization
  Compile the design
  Finite state machine optimization
Synthesis Report and Analysis
Lab Time (Lab2)

dominicyao

<P>自己顶呵呵</P>

moniker

资料怎么就没有精华点的呢，大家多交流啊

kid_007

路过，看看