motorola Professonal verilog coding style 1999年版

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【文件名】:06228@52RD_Professonal Verilog Coding Style.rar
【格　式】:rar
【大　小】:221K
【简　介】:
7.1 Introduction
The general coding standards pertain to IP/VC generation and deal with naming conventions,
documentation of the code and the format, or style, of the code. Conformity to these standards simplifies
reuse by describing insight that is absent from the code, making the code more readable and assuring
compatibility with most tools. Any exceptions to the rules specified in this standard, except as noted, must
be justified and documented.
The methodology standards promote reuse by ensuring a high adaptability among applications. The intent
of this document is to ensure that the gate level implementation is identical to the HDL code as it is
understood by a standard Verilog simulator. Partitioning can affect the ease with which a model can be
adapted to an application. The modeling complex behavior section deals with structures that are typically
difficult to address well in a synthesis environment and are needed to ensure pre- and post-synthesis
consistency. These standards apply to behavioral as well as synthesizable code.
These Verilog-centric standards were developed after an analysis of the Motorola design community, and
are heavily based on the existing Module Board coding guidelines. However, several other sources were
also considered, including VSIA, M-CORE, and Star12.
【目　录】:
Section 7 Verilog HDL Coding
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.2 Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.2.1 Documented References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.2.2 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.1 File Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2 Naming of HDL Code Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.4 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.4.1 File Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.4.2 Additional Construct Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.4.3 Other Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.5 Code Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
7.6 Module Partitioning & Reusability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.7 Modeling Complex Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
7.8 General Coding Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
7.9 Standards for Structured Test Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
7.10 General Standards for Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Appendix A
A.1 Example Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
List of Figures
Figure 7-1 Verilog File Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Figure 7-2 Verilog Functions, User-defined Primitives and Tasks Header . . . . . . . . . . . . 7-16
Figure 7-3 Verilog Coding Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
Figure 7-4 Clock Domain Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
Figure 7-5 Partition Asynchronous Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Figure 7-6 Scan Support for Mixed Latch/Flip-Flop Designs . . . . . . . . . . . . . . . . . . . . . . 7-27