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发表于 2006-2-20 15:08:00
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his paper details efficient Verilog coding styles to infer synthesizable state machines. HDL
considerations such as advantages and disadvantages of one-always block FSMs Vs. two-always
block FSMs are described.
<B>Introduction
Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is a
great paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper also
offers in-depth background concerning the origin of specific state machine types.
This paper, "State Machine Coding Styles for Synthesis," details additional insights into state
machine design including coding style approaches and a few additional tricks.</B>
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