IEEE Standard for SystemVerilog

robertqi

IEEE Standard for SystemVerilog—
Unified Hardware Design, Specification,
and Verification Language

【文件名】:08628@52RD_ieee_std_1800_standard_for_systemverilog_4844.rar
【格　式】:rar
【大　小】:3541K
【简　介】:Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
Approved 8 November 2005
IEEE-SA Standards Board
Abstract: This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware
description language (HDL) to aid in the creation and verification of abstract architectural level
models. It also includes design specification methods, embedded assertions language, testbench
language including coverage and an assertions application programming interface (API), and a
direct programming interface (DPI). This standard enables a productivity boost in design and
validation and covers design, simulation, validation, and formal assertion-based verification flows.
Keywords: assertions, design automation, design verification, hardware description language,
HDL, PLI, programming language interface, SystemVerilog, Verilog, Verilog programming
interface, VPI
【目　录】: