大家帮忙看个翻译对不对，多谢了

stillever

This pushes us to carefully wire this interface with following rules

• Blend system clock (Strip line).
• Wire data and clock on separated layer (internal layer for clocks).
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1，系统时钟走成带状线 （blend查了是混合的意思，比较困惑）
2，数据线和时钟线分在不同层走线