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发表于 2008-6-17 10:07:49
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1 Overview......................................................................................................... 16
1.1 Scope and intended audience...................................................................................... 16
1.2 Application description............................................................................................... 16
1.3 MSM6280 device features .......................................................................................... 21
1.3.1 MSM6280 device general features.................................................................... 23
1.3.2 HSDPA features ................................................................................................ 23
1.3.3 WCDMA R99 features...................................................................................... 24
1.3.4 GSM features..................................................................................................... 25
1.3.5 GPRS features ................................................................................................... 25
1.3.6 EDGE features................................................................................................... 25
1.3.7 MSM6280 device audio processing features..................................................... 26
1.3.8 MSM6280 microprocessor subsystem .............................................................. 26
1.3.9 Supported interface features.............................................................................. 27
1.3.10 Supported multimedia features........................................................................ 27
1.4 MSM6280 ASIC overview ......................................................................................... 30
2 Multimedia Applications ............................................................................... 33
2.1 Mobile display digital interface .................................................................................. 33
2.1.1 MDDI overview ................................................................................................ 33
2.1.2 MDDI system architecture overview................................................................. 33
2.1.2.1 Terminology............................................................................................. 33
2.1.2.2 MDDI interface types .............................................................................. 33
2.1.2.3 MDDI data and strobe.............................................................................. 34
2.1.2.4 MDDI I/O pads interface ......................................................................... 35
2.2 Mobile display processor ............................................................................................ 37
2.2.1 Overview ........................................................................................................... 37
2.2.2 Features ............................................................................................................. 37
2.2.3 MDP LCD module interface ............................................................................. 39
2.2.4 Hardware architecture ....................................................................................... 40
2.2.4.1 Major blocks within the MDP ................................................................. 40
2.2.5 MDP-related design considerations................................................................... 42
2.3 Camera module interface ............................................................................................ 43
2.3.1 Overview ........................................................................................................... 43
2.3.2 Camera module interface................................................................................... 43
2.3.2.1 General description.................................................................................. 43
2.4 Clock requirements ..................................................................................................... 46
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 3 QUALCOMM Proprietary
2.4.1 CAMCLK_PO................................................................................................... 46
2.4.2 Output data format and timing .......................................................................... 46
2.4.3 External synchronization mode functional timing ............................................ 47
2.4.4 New interface and VFE hardware ..................................................................... 48
2.4.5 Multimedia applications using the camera interface ......................................... 48
2.4.5.1 Qcamera................................................................................................... 48
2.4.5.2 Qcamcorder.............................................................................................. 49
2.4.5.3 Qtv ........................................................................................................... 49
2.4.5.4 Qvideophone............................................................................................ 49
2.5 SD/MMC card interface.............................................................................................. 49
2.5.1 Introduction ....................................................................................................... 49
2.5.2 Interface description.......................................................................................... 50
2.5.3 Interface capabilities.......................................................................................... 50
2.5.4 Interface timing ................................................................................................. 51
2.5.5 Clock output ...................................................................................................... 51
2.5.6 SDIO interface................................................................................................... 52
2.5.7 Detect Mechanism............................................................................................. 52
3 ARM Microprocessor and Peripherals......................................................... 53
3.1 AHB system................................................................................................................ 53
3.1.1 AHB buses......................................................................................................... 54
3.1.2 Arbitration ......................................................................................................... 55
3.2 Features....................................................................................................................... 55
3.3 ARM926EJ-S.............................................................................................................. 55
3.3.1 Features ............................................................................................................. 55
3.3.2 Burst access ....................................................................................................... 56
3.4 Memory map and memory map decoder .................................................................... 56
3.4.1 Memory map ..................................................................................................... 57
3.5 Reset and pause........................................................................................................... 57
3.6 Watchdog timer........................................................................................................... 59
3.6.1 Sleep mode ........................................................................................................ 59
3.6.2 Non-sleep mode................................................................................................. 59
3.6.3 General-purpose timer operation....................................................................... 60
3.7 Boot methodology....................................................................................................... 60
3.7.1 Introduction ....................................................................................................... 60
3.7.2 AHB bus memory map...................................................................................... 60
3.7.3 BOOT pin requirements .................................................................................... 62
3.7.4 Hardware support .............................................................................................. 64
3.7.4.1 Boot sequencer......................................................................................... 64
3.7.4.2 Failed trusted boot register....................................................................... 65
3.7.5 Boot-up procedure............................................................................................. 65
3.7.5.1 Trusted boot with NAND flash................................................................ 65
3.7.5.2 Normal boot from NAND flash ............................................................... 66
3.7.6 Other requirements ............................................................................................ 66
3.7.7 MSM device reset scheme summary................................................................. 67
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 4 QUALCOMM Proprietary
4 Memory Interface........................................................................................... 68
4.1 Overview..................................................................................................................... 68
4.2 External bus interface 1 .............................................................................................. 69
4.2.1 Memories supported on EBI1............................................................................ 69
4.2.2 EBI1 system ...................................................................................................... 69
4.2.2.1 Boot-up configuration.............................................................................. 71
4.2.2.2 Chip selects.............................................................................................. 71
4.2.2.3 Switching memory controllers................................................................. 72
4.2.3 External memory controller............................................................................... 72
4.2.4 MPMC overview............................................................................................... 72
4.2.4.1 Requirements ........................................................................................... 73
4.2.4.2 System requirements................................................................................ 73
4.2.4.3 Software requirements ............................................................................. 74
4.2.4.4 Hardware requirements............................................................................ 74
4.2.5 EBI1 clock control block................................................................................... 75
4.3 External bus interface 2 .............................................................................................. 76
4.3.1 Features ............................................................................................................. 77
4.3.2 Chip selects ....................................................................................................... 77
4.3.3 Access types ...................................................................................................... 78
4.3.4 EBI2 system ...................................................................................................... 78
4.3.5 EBI2 external memory controller (asynchronous devices) ............................... 79
4.3.5.1 Features.................................................................................................... 79
4.3.5.2 Boot-up specification............................................................................... 80
4.3.6 Configuration registers ...................................................................................... 80
4.3.6.1 Access description ................................................................................... 80
4.3.6.2 Wait cycles............................................................................................... 80
4.3.6.3 Hold cycles .............................................................................................. 81
4.3.6.4 Recovery cycles ....................................................................................... 81
4.3.6.5 CS_SETUP cycles ................................................................................... 81
4.3.7 External memory controller (LCD support) ...................................................... 81
4.3.7.1 Features.................................................................................................... 81
4.3.7.2 Configuration registers ............................................................................ 82
4.3.7.3 Access description ................................................................................... 82
4.3.7.4 LCD_E_SETUP....................................................................................... 82
4.3.7.5 LCD_E_HIGH......................................................................................... 83
4.3.8 NAND flash memory interface ......................................................................... 83
4.3.8.1 Overview.................................................................................................. 83
4.3.8.2 NAND controller architecture.................................................................. 84
4.3.8.3 Support for two NAND flash devices...................................................... 85
4.3.8.4 ECC for NAND 8/16-bit interface (512B page) ...................................... 85
4.3.8.5 ECC for NAND 8/16-bit interface (2 kB page) ....................................... 87
4.3.8.6 EBI2 interface access arbitration ............................................................. 88
5 RF Interface.................................................................................................... 91
5.1 MSM6280 chipset RF interfaces ................................................................................ 92
5.1.1 SBI..................................................................................................................... 92
5.1.2 Receiver functions............................................................................................. 93
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 5 QUALCOMM Proprietary
5.1.3 Transmitter functions ........................................................................................ 93
5.1.4 GSM transmitter functions ................................................................................ 94
5.1.4.1 GSM PA control signal............................................................................ 94
5.1.4.2 Dual-band TX VCO control signal .......................................................... 94
5.1.5 UMTS transmitter functions.............................................................................. 95
5.1.6 Off-chip VCTCXO functions............................................................................ 95
5.1.7 Antenna control signal....................................................................................... 96
5.1.8 GRFC allocation................................................................................................ 97
5.1.9 PM6650-2 interface........................................................................................... 97
6 Stereo Wideband CODEC ............................................................................. 99
6.1 Audio connections .................................................................................................... 102
6.2 Tx path inputs and gains ........................................................................................... 104
6.3 Rx path outputs ......................................................................................................... 104
6.4 Audio DSP ................................................................................................................ 105
6.4.1 Tx path audio DSP .......................................................................................... 105
6.4.2 Rx path audio DSP .......................................................................................... 106
6.5 Recommended gain settings ..................................................................................... 107
6.6 PCM interface........................................................................................................... 108
6.6.1 Auxiliary PCM ................................................................................................ 108
6.6.2 Primary PCM................................................................................................... 108
6.6.3 Using AUX_PCM to interface with an external stereo DAC.......................... 109
6.6.4 SDAC_CLK setting......................................................................................... 110
6.7 External analog interface details............................................................................... 111
6.7.1 Handset interfaces ........................................................................................... 111
6.7.2 Headset interfaces............................................................................................ 111
6.7.3 Auxiliary I/O interface (car-kit) ...................................................................... 115
6.7.4 Line input to output audio ............................................................................... 116
6.8 Interface to an external speaker amplifier (PM6650) ............................................... 116
7 UART, USIM, and USB Interfaces............................................................... 117
7.1 UART interface......................................................................................................... 117
7.1.1 General description.......................................................................................... 117
7.1.2 UART transmit description ............................................................................. 118
7.1.3 UART receive description............................................................................... 118
7.1.4 UART features and usage................................................................................ 119
7.1.4.1 General features ..................................................................................... 119
7.1.5 UART interrupt control ................................................................................... 120
7.1.6 UART2 and UART3 configuration................................................................. 120
7.2 USIM interface ......................................................................................................... 121
7.2.1 General description.......................................................................................... 121
7.2.2 USIM interface description ............................................................................. 122
7.2.3 USIM implementation..................................................................................... 122
7.3 USB on-the-go interface ........................................................................................... 123
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 6 QUALCOMM Proprietary
7.3.1 Introduction ..................................................................................................... 123
7.3.2 OTG controller architecture ............................................................................ 124
7.3.2.1 Supported transactions........................................................................... 124
7.3.2.2 Host vs. peripheral operation ................................................................. 124
7.3.2.3 Endpoints ............................................................................................... 126
7.3.2.4 Pin MUX architecture............................................................................ 127
7.3.3 Transceiver interfaces...................................................................................... 127
7.3.3.1 Three-wire interface............................................................................... 127
7.3.3.2 PMIC interface....................................................................................... 129
7.4 Carkit interface ......................................................................................................... 130
8 User Interface............................................................................................... 131
8.1 Keypad interface ....................................................................................................... 131
8.2 Ringer........................................................................................................................ 132
8.3 M/N counter.............................................................................................................. 134
8.4 General purpose clock............................................................................................... 135
8.4.1 Overview ......................................................................................................... 135
8.4.2 General characteristics .................................................................................... 136
8.4.3 Implementation................................................................................................ 136
8.5 HKADC.................................................................................................................... 136
8.5.1 Analog input voltage range ............................................................................. 136
8.5.2 HKADC operation........................................................................................... 137
8.5.3 HKADC conversion time ................................................................................ 138
8.5.4 HKADC analog interface considerations ........................................................ 139
9 Clock Regime............................................................................................... 141
9.1 TCXO........................................................................................................................ 141
9.2 CODEC PLL............................................................................................................. 141
9.3 Sleep crystal circuit for 32.768 kHz ......................................................................... 141
9.4 USB oscillator circuit for 48 MHz............................................................................ 144
9.5 Subsystem clock regimes.......................................................................................... 145
9.5.1 Clock block architecture.................................................................................. 145
9.5.2 Clock regimes.................................................................................................. 146
10 JTAG Interface, Mode Select, and Emulation Considerations............... 147
10.1 JTAG interface........................................................................................................ 147
10.1.1 JTAG standard overview............................................................................... 147
10.1.2 MSM device JTAG interface ........................................................................ 148
10.1.3 Test access port ............................................................................................. 149
10.1.3.1 TCK ..................................................................................................... 149
10.1.3.2 TMS ..................................................................................................... 149
10.1.3.3 TDI....................................................................................................... 150
10.1.3.4 TDO..................................................................................................... 150
10.1.3.5 TRST_N............................................................................................... 150
10.1.4 TAP controller............................................................................................... 150
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 7 QUALCOMM Proprietary
10.1.5 Data registers................................................................................................. 151
10.1.5.1 Device identification register............................................................... 151
10.1.5.2 Bypass register..................................................................................... 151
10.1.5.3 Boundary-scan register ........................................................................ 152
10.1.6 Instruction register......................................................................................... 152
10.1.7 JTAG selection.............................................................................................. 153
10.2 Embedded trace macrocell...................................................................................... 154
10.3 ETM overview........................................................................................................ 154
10.4 ETM architecture .................................................................................................... 156
10.5 ETM features .......................................................................................................... 156
10.5.1 16-bit normal mode ....................................................................................... 157
10.5.2 8-bit deMUX mode (recommended ETM mode).......................................... 157
10.5.3 Half-rate clocking.......................................................................................... 157
10.6 ETM implementation on the MSM devices............................................................ 158
11 Transport Stream Interface for DMB........................................................ 159
11.1 TSIF features........................................................................................................... 160
11.2 TSIF connections .................................................................................................... 161
11.3 TSIF hardware architecture..................................................................................... 161
11.4 TSIF external hardware interface modes ................................................................ 163
11.4.1 TSIF mode 1.................................................................................................. 163
11.4.2 TSIF mode 2.................................................................................................. 165
11.4.3 Sampling optional TSIF signals .................................................................... 165
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 8 QUALCOMM Proprietary
Figures
Figure 1-1 MSM6280 system functional diagram (Platform 3U)................................................. 22
Figure 2-1 MDDI physical connection of host and display, type-1.............................................. 34
Figure 2-2 MDDI high level block diagram ................................................................................. 35
Figure 2-3 MDDI top level block diagram ................................................................................... 36
Figure 2-4 Block diagram of the MDP-to-LCD interface............................................................. 39
Figure 2-5 Major functional blocks within the MDP.................................................................... 40
Figure 2-6 Camera interface ......................................................................................................... 43
Figure 2-7 MSM6280 camera interface........................................................................................ 44
Figure 2-8 Horizontal and vertical synchronization signals ......................................................... 47
Figure 2-9 Frame start condition................................................................................................... 47
Figure 2-10 Frame start condition with invalid lines after VSYNC............................................. 47
Figure 2-11 The SD interface connections on the MSM6280 device........................................... 50
Figure 3-1 AHB system architecture ............................................................................................ 54
Figure 3-2 Reset generation.......................................................................................................... 58
Figure 3-3 Watchdog timer configuration .................................................................................... 59
Figure 3-4 Trusted boot hardware support.................................................................................... 64
Figure 4-1 EBI1 hierarchy and connections to external memory ................................................. 70
Figure 4-2 MPMC write timing diagram...................................................................................... 75
Figure 4-3 MPMC read timing diagram ....................................................................................... 75
Figure 4-4 EBI1 external clock generation................................................................................... 76
Figure 4-5 EBI2 boot up time specification w/ NAND2_FLASH_READY tied to logic 1......... 80
Figure 4-6 NAND controller block diagram................................................................................. 85
Figure 4-7 Page format description (8-bit/16-bit – 512 B/page)................................................... 86
Figure 4-8 Page format description – MSM6280 (8-bit/16-bit – 2kB/page) ................................ 87
Figure 4-9 Interface connection NAND flash and MSM6280 device .......................................... 90
Figure 5-1 Platform 3U RF interface diagram.............................................................................. 98
Figure 6-1 CODEC, audio DSP, and PCM interface.................................................................. 101
Figure 6-2 Analog CODEC front end with audio connections................................................... 102
Figure 6-3 Slope filter response.................................................................................................. 105
Figure 6-4 High-pass filter response........................................................................................... 106
Figure 6-5 Typical handset microphone and earphone interfaces .............................................. 111
Figure 6-6 Basic headset interfaces ............................................................................................ 112
Figure 6-7 Stereo earphone interfaces ........................................................................................ 112
Figure 6-8 Mono-differential earphone interface........................................................................ 113
Figure 6-9 Stereo earphone interfaces using the capless driver.................................................. 113
Figure 6-10 Basic microphone with switch ................................................................................ 114
Figure 6-11 Microphone with switch using the capless driver ................................................... 114
Figure 6-12 Microphone with separate switch output pin .......................................................... 115
Figure 6-13 Typical analog carkit application ............................................................................ 115
Figure 6-14 Typical line-in to line-out usage.............................................................................. 116
Figure 6-15 Using the PM6650 speaker driver........................................................................... 116
Figure 7-1 UART block diagram................................................................................................ 117
Figure 7-2 Multiplexing arrangement for UART2 and UART3................................................. 121
Figure 7-3 OTG architecture....................................................................................................... 124
Figure 7-4 Pin MUX architecture ............................................................................................... 127
Figure 7-5 Three-wire interface .................................................................................................. 128
Figure 7-6 PMIC interface.......................................................................................................... 129
Figure 7-7 Carkit interface.......................................................................................................... 130
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 9 QUALCOMM Proprietary
Figure 8-1 KEYSENSE[4:0] circuits.......................................................................................... 131
Figure 8-2 Ringer generation circuit........................................................................................... 132
Figure 8-3 External driver circuit example ................................................................................. 132
Figure 8-4 GP_MN block diagram ............................................................................................. 134
Figure 8-5 General HKADC conversion process ....................................................................... 138
Figure 8-6 Equivalent circuits for HKADC input and external voltage sources ........................ 140
Figure 9-1 Sleep oscillator circuit with passive crystal .............................................................. 143
Figure 9-2 USB oscillator circuit................................................................................................ 144
Figure 9-3 Clock block architecture ........................................................................................... 146
Figure 10-1 MSM device JTAG interface .................................................................................. 148
Figure 10-2 JTAG interface block diagram ................................................................................ 149
Figure 10-3 Data structure for device identification register...................................................... 151
Figure 10-4 Typical structure of a boundary-scan cell ............................................................... 152
Figure 10-5 JTAG and MSM pin connections for selecting MSM BSDL scan chain,
WDOG disabled (MSM6280 example) ....................................................................................... 153
Figure 10-6 JTAG and MSM pin connections for selecting ARM JTAG, WDOG
disabled (MSM6280 example)..................................................................................................... 154
Figure 10-7 Example debugging environment using ETM ........................................................ 155
Figure 10-8 Basic ETM architecture........................................................................................... 156
Figure 10-9 ETM 8-bit deMUX mode........................................................................................ 157
Figure 11-1 MSM6280 DMB handset architecture .................................................................... 160
Figure 11-2 TSIF hardware architecture..................................................................................... 162
Figure 11-3 TSIF system memory packet................................................................................... 163
Figure 11-4 TSIF mode 1 signals and timing ............................................................................. 164
Figure 11-5 TSIF mode 2 signals and timing ............................................................................. 165
Figure 11-6 Sampling optional TSIF signals .............................................................................. 165
Tables
Table 1-1 Summary of MSM6280 device features....................................................................... 29
Table 2-1 MDDI I/O pad interface specification.......................................................................... 36
Table 2-2 I/O and power supply signals to/from the MSM6280 device....................................... 44
Table 2-3 Qcamera capabilities summary..................................................................................... 49
Table 2-4 Qcamcorder capabilities summary ............................................................................... 49
Table 2-5 SD interface signals and GPIOs used ........................................................................... 50
Table 2-6 SD interface timing parameters .................................................................................... 51
Table 2-7 SD interface speed capability ....................................................................................... 51
Table 3-1 ARM burst transfer support.......................................................................................... 56
Table 3-2 Memory map (for NAND boot).................................................................................... 57
Table 3-3 MSM6280 decoder HSEL signal descriptions ............................................................. 61
Table 3-4 Boot-up pins ................................................................................................................. 63
Table 4-1 Memories supported on EBI1 by the two memory controllers..................................... 71
Table 4-2 Supported primary EBI1 memory configurations ........................................................ 71
Table 4-3 Register names associated with the EBI1 chip selects ................................................. 72
Table 4-4 EBI2 chip selects .......................................................................................................... 77
Table 4-5 Access types by chip select .......................................................................................... 78
Table 4-6 EBI2 priority options.................................................................................................... 79
Table 4-7 Chip-select configuration registers for EBI2 external memory controller ................... 80
Table 4-8 Chip select configuration registers for EBI2 external memory controller (LCD)........ 82
Table 4-9 ECC allocation – 8-bit NAND interface (512 B page)................................................. 86
MSM6280™ Mobile Station Modem™ User Guide Contents
80-V6968-3 Rev. A 10 QUALCOMM Proprietary
Table 4-10 ECC allocation – 16-bit NAND interface (512 B page)............................................. 86
Table 4-11 ECC allocation in 8-bit NAND interface (2K page) .................................................. 87
Table 4-12 ECC allocation in 16-bit NAND interface (2K page) ................................................ 88
Table 5-1 Platform 3U RFIC receive parameters – MSM-controlled via SBI.............................. 93
Table 5-2 GSM/GPRS/EGPRS OLL VCO control signals .......................................................... 94
Table 5-3 Platform 3U antenna switch control signals ................................................................. 96
Table 5-4 GRFC allocation on Platform 3U and RFCMOS Platform B....................................... 97
Table 6-1 Audio connections ...................................................................................................... 103
Table 6-2 GPIO assignments for AUX_PCM and SDAC interfaces.......................................... 109
Table 6-3 Sampling frequency and SDAC_CLK rates............................................................... 110
Table 7-1 GPIO pins for USIM/UART2..................................................................................... 122
Table 7-2 Three-wire transmit operation ..................................................................................... 128
Table 7-3 Three-wire receive operation....................................................................................... 128
Table 8-1 Standard DTMF frequencies and ringer programming values ................................... 133
Table 8-2 Keypad frequencies .................................................................................................... 134
Table 8-3 Using GP_MN as a digital output............................................................................... 135
Table 8-4 I2C pins ...................................................................................................................... 136
Table 8-5 MSM6280 ADC transfer function.............................................................................. 137
Table 8-6 ADC timing for TCXO/4 clock source....................................................................... 138
Table 8-7 ADC timing for TCXO clock source.......................................................................... 139
Table 8-8 Recommended Rs maximum values........................................................................... 140
Table 9-1 Sleep oscillator inverter – relative gain settings ......................................................... 142
Table 9-2 Suggested SLEEP_OSC_CTL settings of bits 11:8 ................................................... 142
Table 9-3 Recommended USB_OSC_CTL settings................................................................... 145
Table 9-4 Descriptions of clock origins...................................................................................... 146
Table 10-1 Device identification register.................................................................................... 151
Table 10-2 GPIO[66:42] signals in ETM mode.......................................................................... 158
Table 11-1 Digital Mobile Broadcast standards ......................................................................... 159
Table 11-2 TSIF connections...................................................................................................... 161
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