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【文件名】:071226@52RD_An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge.pdf
【格 式】:pdf
【大 小】:408K
【简 介】:PLL的环路滤波器参数如何计算?看了就明白了
【目 录】:The high performance of today’s digital phase-lock loop
makes it the preferred choice for generation of stable, low
noise, tunable local oscillators in wireless communications
applications. This paper investigates the design of passive
loop filters for Frequency Synthesizers utilizing a Phase-
Frequency Detector and a current switch charge pump such
as National Semiconductor’s PLLatinum™ Series. Passive
filter design for a TYPE II third order phase-lock loop is
discussed in depth, with some discussion of higher order
filters included. Specific test results are presented for a GSM
synthesizer design. Optimization of phase-lock loop performance
with respect to different parameters is discussed.
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