ARM 926 TRM

joseph611201

This document is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an overview of the ARM926EJ-S processor.
Chapter 2 Programmer’s Model
Read this chapter for details of the programmer’s model and
ARM926EJ-S registers.
Chapter 3 Memory Management Unit
Read this chapter for details of the Memory Management Unit (MMU)
and address translation process and how to use the CP15 register to
enable and disable the MMU.
Chapter 4 Caches and Write Buffer
Read this chapter for a description of the instruction cache, the data
cache, the write buffer, and the physical address tag RAM.
Chapter 5 Tightly-Coupled Memory Interface
Read this chapter for a description of the Tightly-Coupled Memory
(TCM) interface and how to use the CP15 region register to enable and
disable the caches. It includes examples on how various RAM types can
be connected
【文件名】:071225@52RD_DDI0198D_926_TRM.pdf
【格　式】:pdf
【大　小】:1702K
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