|
Responsibilities include:
Detail design specification and test plan development.
RTL logic design, synthesis and timing closure.
Module and full chip verification, formal verification and equivalence checking.
Work with cross-functional teams (hardware, software, diagnostics, signal integrity group).
Assist in prototype bring up and verification in the lab.
Skills Required
Experience in high performance ASIC design experience from start to finish.
Good understanding in ASIC methodologies and flows.
Working knowledge using HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
Excellent written and verbal communications, team and people skills.
Self motivated, ability to work independently with minimal supervision and provides leadership role.
Networking knowledge preferred.
Educational Background
Typically requires MSEE/CS combined with 4+ years of related experience, or BSEE/CS combined with 6+ yrs related experience.
有想法的跟我联系或发简历给我
mail: gary@chinaeejob.com
MSN: gold_bowl@hotmail.com |
|