那位有Cadence仿真的资料

leihubao

求Cadence SI仿真资料

swlee0

【文件名】:09430@52RD_Allegro PCB SI Foundations Training Manual.pdf
【格　式】:pdf
【大　小】:3872K
【简　介】:
【目　录】:




October 21, 2005 Allegro PCB SI Foundations v
Contents
Lesson 1:     Introduction to Allegro PCB SI Design Flow .......................................................................1-1
Cadence PCB Tools Used in This Class........................................................................................1-1
Getting Help ..................................................................................................................................1-2
Allegro PCB SI Design Flow ........................................................................................................1-3
Allegro PCB SI Foundations Lab Flow.........................................................................................1-4
What is Allegro PCB SI 610?........................................................................................................1-5
Allegro PCB SI 610 Window ........................................................................................................1-6
Basic Display Functions: Display Ratsnest ...................................................................................1-7
Basic Display Functions: Color and Visibility ..............................................................................1-8
Getting Information About Objects...............................................................................................1-9
Component Placement.................................................................................................................1-11
Labs .............................................................................................................................................1-12
Lab 1-1:  Basic Allegro PCB SI Features ...................................................................................1-13
Lesson 2:     Allegro PCB SI Design Flow — Pre-placement...................................................................2-1
Allegro PCB SI Design Flow ........................................................................................................2-1
Design Flow—Pre-Placement .......................................................................................................2-2
Board Setup Requirements for Extracting and Applying Topologies...........................................2-3
Database Setup Advisor.................................................................................................................2-4
Database Setup Advisor—Cross Section ......................................................................................2-5
What is the Layout Cross Section?................................................................................................2-6
Defining the Layout Cross Section................................................................................................2-6
Materials Editor .............................................................................................................................2-8
DC Voltages ..................................................................................................................................2-9
Database Setup Advisor—DC Nets.............................................................................................2-10
Device CLASS and PINUSE Properties .....................................................................................2-11
Database Setup Advisor—Device Setup .....................................................................................2-13
Editing the Parts List ...................................................................................................................2-14
Editing Pin Types ........................................................................................................................2-15
Labs .............................................................................................................................................2-16
Lab 2-1:  Board Setup Requirements — Invoking the Database Setup Advisor........................2-17
Lab 2-2:  Board Setup Requirements — Editing the Board Cross Section ................................2-21
Lab 2-3:  Board Setup Requirements — Identifying DC Nets ...................................................2-24
Lab 2-4:  Board Setup Requirements — Device Setup ..............................................................2-27
Lab Summary ..............................................................................................................................2-31
Database Setup Advisor—SI Models ..........................................................................................2-32
Signal Model Assignment Form..................................................................................................2-32
Auto Setup Models ......................................................................................................................2-34
Signal Analysis Library Browser ................................................................................................2-35
Translating and Adding Libraries................................................................................................2-36
The Model Browser .....................................................................................................................2-38
Model Integrity ............................................................................................................................2-40
Model Integrity Features .............................................................................................................2-41
Model Dump/Refresh ..................................................................................................................2-42
Database Setup Advisor—SI Audit.............................................................................................2-43
Allegro PCB SI Foundations Table of Contents
vi Cadence Design Systems, Inc. October 21, 2005
Labs..............................................................................................................................................2-44
Lab 2-5:  Board Setup Requirements — Signal Model Assignment ..........................................2-45
Lesson 3:     Creating a DesignLink...........................................................................................................3-1
Learning Objectives.......................................................................................................................3-1
System-Level Analysis ..................................................................................................................3-1
EBD Models and DML Models.....................................................................................................3-2
A Complete Design Link ...............................................................................................................3-3
System Configuration ....................................................................................................................3-4
Labs................................................................................................................................................3-5
Lab 3-1:  Translating an EBD Model to a SigNoise DML Model................................................3-6
Lab 3-2:  Creating a DesignLink Between a Motherboard and a Board Model .........................3-11
Lab 3-3:  Performing Multi-Board Modeling .............................................................................3-15
Lab 3-4:  Initializing the System Configuration .........................................................................3-20
Lesson 4:     Extracting and Simulating Topologies ..................................................................................4-1
Pre-Route Extraction Setup—Default Model Selection ................................................................4-2
Pre-Route Extraction Setup—Unrouted Interconnect ...................................................................4-3
What are Physical Nets and Xnets? ...............................................................................................4-4
Pre-Route Template Extraction .....................................................................................................4-5
Labs................................................................................................................................................4-6
Lab 4-1:  Unrouted Interconnect Extraction Setup .......................................................................4-7
Lab 4-2:  Pre-Layout Topology Extraction for Analysis ............................................................4-12
SigXplorer 610.............................................................................................................................4-17
SigXplorer Command Tab...........................................................................................................4-19
SigXplorer Parameters Tab..........................................................................................................4-20
SigXplorer Measurements Tab ....................................................................................................4-21
SigXplorer Results Tab................................................................................................................4-22
Starting a SigXplorer Simulation.................................................................................................4-23
Analysis Preferences—Pulse Stimulus........................................................................................4-24
Analysis Preferences—Simulation Parameters ...........................................................................4-25
Analysis Preferences—Simulation Modes ..................................................................................4-27
Analysis Preferences—Measurement Modes ..............................................................................4-28
IO Cell Stimulus Edit...................................................................................................................4-29
IO Cell Stimulus Edit Options.....................................................................................................4-30
Labs..............................................................................................................................................4-31
Lab 4-3:  Setting Up Simulation Preferences and Executing a Reflection Simulation ..............4-32
What is SigWave?........................................................................................................................4-37
SigWave Imports and Exports .....................................................................................................4-39
The SigWave Current Waveforms...............................................................................................4-40
The SigWave Waveform Library ................................................................................................4-42
Delay Measurements—Rising Edge............................................................................................4-43
Delay Measurements—Falling Edge...........................................................................................4-45
Delay Measurements—Other ......................................................................................................4-46
Delay Measurements—Monotonicity..........................................................................................4-47
Directories and Files Created from Simulation ...........................................................................4-48
Labs..............................................................................................................................................4-51
Lab 4-4:  Reflection Simulation Measurements .........................................................................4-52
Lab 4-5:  Extracting Strobe and Other Data bits for Analysis....................................................4-71
Lesson 5:     Determining and Adding Constraints....................................................................................5-1
Table of Contents Allegro PCB SI Foundations
October 21, 2005 Cadence Design Systems, Inc. vii
Solution Space Analysis ................................................................................................................5-2
Solution Space Analysis Step 1 .....................................................................................................5-3
Solution Space Analysis Step 2 .....................................................................................................5-4
Solution Space Analysis Step 3 .....................................................................................................5-5
Solution Space Analysis Step 4 .....................................................................................................5-7
Solution Space Analysis Step 5 .....................................................................................................5-8
Solution Space Analysis Step 6 .....................................................................................................5-9
Creating a Topology ......................................................................................................................5-9
Wiring the Topology ...................................................................................................................5-11
Append Topology ........................................................................................................................5-12
Assigning Strobe Pins..................................................................................................................5-13
Labs .............................................................................................................................................5-15
Lab 5-1:  Appending the Topologies ..........................................................................................5-16
Lab 5-2:  Identifying the Topology as Source Synchronous ......................................................5-22
Accessing the Measurement Expression Editor ..........................................................................5-24
Measurement Expression Editor..................................................................................................5-25
Custom Constraint in the Expression Editor ...............................................................................5-27
Expression Treeview Pop-up Menus...........................................................................................5-28
Measurement References.............................................................................................................5-30
PinParameter Function ................................................................................................................5-31
Waveform Measurement Functions.............................................................................................5-32
Math Functions ............................................................................................................................5-34
Waveform Function — RangeCrossingTime Function...............................................................5-35
Labs .............................................................................................................................................5-36
Lab 5-3:  Writing and Importing Custom Measurements...........................................................5-37
Parametric Sweeps.......................................................................................................................5-41
Setting Sweep Parameters ...........................................................................................................5-42
The Sweep Manager ....................................................................................................................5-43
The Sweep Report .......................................................................................................................5-44
Labs .............................................................................................................................................5-45
Lab 5-4:  Determining Constraints Used in Topologies .............................................................5-46
Lab 5-5:  Setting Custom Stimulus.............................................................................................5-51
Lab 5-6:  Assigning Parametric Sweeps .....................................................................................5-54
Lab 5-7:  Executing Parametric Sweep Simulations ..................................................................5-65
Constraints Introduction ..............................................................................................................5-72
Topology Template Constraints ..................................................................................................5-73
Assigning Switch/Settle Constraints ...........................................................................................5-75
Assigning the Prop Delay Constraints.........................................................................................5-76

tiehong_liu

tai gui le

TIM207

是挺贵的

kevenyang

kan bu dao?