Modeling Jitter in PLL-based Frequency Synthesizers

veryrd

【文件名】:0617@52RD_Modeling Jitter in PLL-based Frequency Synthesizers　　.rar
【简　介】:
Version 4, 1 April 2003 A methodology is presented for modeling the jitter in a Phase-Locked Loop (PLL) that
is both accurate and efficient. The methodology begins by characterizing the noise
behavior of the blocks that make up the PLL using transistor-level simulation. For each
block, the jitter is extracted and provided as a parameter to behavioral models for inclusion
in a high-level simulation of the entire PLL. This approach is efficient enough to be
applied to PLLs acting as frequency synthesizers with large divide ratios.
Last updated on January 1, 2004. You can find the most recent version at www.designersguide.
com. Contact the author via e-mail at ken@designers-guide.com.
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<B>1 Introduction</B>Phase-locked loops (PLLs) are used in wireless receivers to implement a variety of
functions, such as frequency synthesis, clock recovery, and demodulation. One of the
major concerns in the design of PLLs is noise or jitter performance. Jitter from the PLL
directly acts to degrade the noise floor and selectivity of a transceiver.
Demir proposed an approach for modeling PLLs whereby a PLL is described using high
level behavioral models [1,2]. The models are written such that they include jitter in an
efficient way. He also devised a powerful new simulation algorithm that is capable of
characterizing the circuit-level noise behavior of blocks that make up a PLL that is
based on solving a set of nonlinear stochastic differential equations [3,5]. Finally, he
gave formulas that can be used to convert the results of the noise simulations on the
individual blocks into values for the jitter parameters for the corresponding behavioral
models [6]. This approach provides accurate and efficient prediction of PLL jitter
behavior once the noise behavior of the blocks has been characterized. However, it
requires the use of an experimental simulator that is not readily available.
This paper presents the relevant ideas of Demir, but while he focussed on presenting the
conceptual aspects of modeling and simulating jitter in PLLs, this paper concentrates
more on the practical aspects. It presents all the information a designer would need to
predict the noise and jitter of a PLL synthesizer. This paper is an enhanced version of
two previous papers [13,14]. The jitter extraction methodology is based on the commercially
available Spectre&#63194;RF1 simulator [23,24] and presents behavioral models for Verilog-
A2, a standard, non-proprietary analog behavioral modeling language [7,18]. Both
SpectreRF and Verilog-A are options to the Spectre circuit simulator [12], available
from Cadence Design Systems.3
【目　录】:
1.intrudction
2.frequency synthesis
3.jitter
4synchronous jitter
5accumulating jitter
6.jitter of a pll
7.Modeling plls with jitter
8.simulation and analysis
9 example
10 conclution
【格　式】:rar
【大　小】:250K

maxswell

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