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【文件名】:071016@52RD_PhaseLockedLoop_2006--DESIGN.pdf
【格 式】:pdf
【大 小】:1242K
【简 介】:
【目 录】:
Our team chose to do a complete mixed signal IC design process. With this purpose, we
decided to design a Phase Locked Loop (PLL) because the design process would incorporate
topics from digital, analog, IC design, and control systems theory. This range of topics is an
adequate way to incorporate the primary electrical engineering theories into one project.
A PLL is a closed loop frequency system that locks the phase of an output signal to an
input reference signal. The term “lock” refers to a constant or zero phase difference between two
signals. The signal from the feedback path, ffb, is compared to the input reference signal, fref,
until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and
the signal is sent to each component in the loop to correct the phase difference. These
components consist of the Phase Frequency Detector (PFD), the charge pump (CP), the low pass
filter (LPF), and the voltage controlled oscillator (VCO). The PFD detects any phase differences
in fref and ffb and then generates an error signal. According to that error signal the CP either
increases or decreases the amount of charge to the LPF. This amount of charge either speeds up
or slows down the VCO. The loop continues in this process until the phase difference between
fref and ffb is zero or constant—this is the locked mode. After the loop has attained a locked
status, the loop still continues in the process but the output of each component is constant. The
output signal, fout, has the same phase and/or frequency as fref.
This design flow process included design and simulation of the components/system and it
also included the VCO layout. The application we chose in designing the PLL was a clock
generator and frequency synthesizer. A clock generator generates a digital clock signal and a
frequency synthesizer generates a frequency that can have a different frequency from the original
reference signal. |
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IP卡
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发表于 2007-10-16 23:46:38
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