IEEE Std 1364-2001 Standard Verilog hardware description language

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Clause 1
—
Overview:
This clause discusses the conventions used in this standard and its contents.
IEEE
HARDWARE DESCRIPTION LANGUAGE Std 1364-2001
Copyright © 2001 IEEE. All rights reserved.
3
Clause 2
—
This clause describes the lexical tokens used in Verilog HDL source text and their conventions.:
This clause describes how to specify and interpret the lexical tokens.
Clause 3
—
Data types:
This clause describes net and variable data types. This clause also discusses the
parameter data type for constant values and describes drive and charge strength of the values on nets.
Clause 4
—
Expressions:
This clause describes the operators and operands that can be used in expressions.
Clause 5
—
Scheduling semantics:
This clause describes the scheduling semantics of the Verilog HDL.
Clause 6
—
Assignments:
This clause compares the two main types of assignment statements in the Verilog
HDL
—
continuous assignments and procedural assignments. It describes the continuous assignment statement
that drives values onto nets.
Clause 7
—
Gate and switch level modeling:
This clause describes the gate and switch level primitives and
logic strength modeling.
Clause 8
—
User-defined primitives (UDPs):
This clause describes how a primitive can be defined in the
Verilog HDL and how these primitives are included in Verilog HDL models.
Clause 9
—
Behavioral modeling:
This clause describes procedural assignments, procedural continuous
assignments, and behavioral language statements.
Clause 10
—
Tasks and functions:
This clause describes tasks and functions
—
procedures that can be called
from more than one place in a behavioral model. It describes how tasks can be used like subroutines and
how functions can be used to define new operators.
Clause 11
—
Disabling of named blocks and tasks:
This clause describes how to disable the execution of a
task and a block of statements that has a specified name.
Clause 12
—
Hierarchical structures:
This clause describes how hierarchies are created in the Verilog HDL
and how parameter values declared in a module can be overridden. It describes how generated instantiations
can be used to do conditional or multiple instantiations in a design.
Clause 13
—
Configuring the contents of a design:
This clause describes how to configure the contents of a
design.
Clause 14
—
Specify blocks:
This clause describes how to specify timing relationships between input and
output ports of a module.
Clause 15
—
Timing checks:
This clause describes how timing checks are used in specify blocks to determine
if signals obey the timing constraints.
Clause 16
—
Backannotation using the Standard Delay Format (SDF):
This clause describes syntax and
semantics of Standard Delay Format (SDF) constructs.
Clause 17
—
System tasks and functions:
This clause describes the system tasks and functions.
Clause 18
—
Value change dump (VCD) files:
This clause describes the system tasks associated with Value
Change Dump (VCD) file, and the format of the file.
Clause 19
—
Compiler directives:
This clause describes the compiler directives.
Clause 20
—
PLI overview:
This clause previews the C language procedural interface standard (Programming
Language Interface or PLI) and interface mechanisms that are part of the Verilog HDL.
Clause 21
—
PLI TF and ACC interface mechanism
This clause describes the interface mechanism that provides a means for users to link PLI task/function (TF)
routine and access (ACC) routine applications to Verilog software tools.
Clause 22
—
Using ACC routines:
This clause describes the ACC routines in general, including how and
why to use them.
Clause 23
—
ACC routine definitions:
This clause describes the specific ACC routines, explaining their
function, syntax, and usage.
Clause 24
—
Using TF routines:
This clause provides an overview of the types of operations that are done
with the TF routines.
Clause 25
—
TF routine definitions:
This clause describes the specific TF routines, explaining their function,
syntax, and usage.
Clause 26
—
Using VPI routines:
This clause provides an overview of the types of operations that are done
with the Verilog Programming Interface (VPI) routines.
Clause 27
—
VPI routine definitions:
This clause describes the VPI routines.
Annex A—Formal syntax definition: This normative annex describes, using BNF, the syntax of the Verilog
HDL.
Annex B—List of keywords: This normative annex lists the Verilog HDL keywords.
Annex C—System tasks and functions: This informative annex describes system tasks and functions that
are frequently used, but that are not part of the standard.
Annex D—Compiler directives: This informative annex describes compiler directives that are frequently
used, but that are not part of the standard.
Annex E—acc_user.h: This normative annex provides a listing of the contents of the acc_user.h file.
Annex F—veriuser.h: This normative annex provides a listing of the contents of the vpi_user.h file.
Annex G—vpi_user.h: This normative annex provides a listing of the contents of the veriuser.h file.
Annex H—Bibliography: This informative annex contains bibliographic entries pertaining to this standard.

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