展讯6600管脚定义资料

szfhao

【文件名】:0799@52RD_芯片脚位编号SC6600B7 Device Specification.pdf
【格　式】:pdf
【大　小】:1468K
【简　介】:6600各引脚功能共192页
【目　录】:1 Overview.............................................................................................................................................11

1.1 SC6600 Features.......................................................................................................................11
1.2 Applications ...............................................................................................................................12
1.3 General Description...................................................................................................................12
1.4 Block Diagram ...........................................................................................................................14
2 Pin Information....................................................................................................................................15
2.1 Pin Type Description..................................................................................................................15
2.2 Pin List by Pin Numbers ............................................................................................................15
2.3 Pin List by Functions..................................................................................................................19
2.4 Package Pin Map.......................................................................................................................23
2.5 Pad Driving Strength..................................................................................................................24
2.6 Pad Weak Pull-Up .....................................................................................................................24
3 Electrical Specifications......................................................................................................................25
3.1 DC Specifications ......................................................................................................................25
3.1.1 Absolute Maximum Ratings...................................................................................................25
3.1.2 Recommended Operating Conditions...................................................................................25
3.1.3 Thermal Characteristics ........................................................................................................25
3.1.4 DC Characteristics ................................................................................................................26
3.2 AC Specifications......................................................................................................................27
3.2.1 Master Clock MCLKI Timing..................................................................................................27
3.2.2 Three-Wire Serial Interface Timing .......................................................................................28
3.2.3 S8 Serial Port Interface Timing .............................................................................................32
3.2.4 JTAG Timing.........................................................................................................................33
3.3 Performance Specifications.......................................................................................................34
3.3.1 Baseband ..............................................................................................................................34
3.3.1.1 Baseband Transmit Path..............................................................................................34
3.3.1.2 Baseband Receive Path...............................................................................................35
3.3.2 Voice Band ............................................................................................................................35
3.3.2.1 Voice Band Uplink ADC................................................................................................35
3.3.2.2 Voice Band Downlink DAC...........................................................................................36
3.3.3 Phase-Locked Loop (PLL).....................................................................................................36
3.3.4 Auxiliary Digital-to-Analog Converters ..................................................................................37
3.3.4.1 Automatic Frequency Control (AFC) ............................................................................37
3.3.4.2 RFPower Ramping Control DAC.................................................................................37
3.3.5 Auxiliary Analog-to-Digital Converter....................................................................................37
3.3.6 LDO......................................................................................................................................38
4 Software Interface...............................................................................................................................39
4.1 Address Maps...........................................................................................................................39
4.1.1 ARM Memory Map ................................................................................................................39
4.1.2 DSP Address Maps ...............................................................................................................41
4.1.2.1 DSP Program Address Map.........................................................................................41
4.1.2.2 DSP Data Address Map................................................................................................41
4.2 Quick Reference by Address.....................................................................................................42
4.2.1 ARM Control Registers..........................................................................................................42
4.2.1. External Memory Control Registers..............................................................................42
4.2.1. Bus Monitor Control Registers......................................................................................43
4.2.1. Chip ID Register ...........................................................................................................44
4.2.1. Interrupt Control Registers............................................................................................44
4.2.1. Timer Control Registers................................................................................................45
4.2.1. Remap and Pause Control Registers...........................................................................47
4.2.1. UART0, UART1 Registers............................................................................................47

LIANJITONGXU

OK，已经下了，看看再说