THe VHDL-Cookbook

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Contents
1. Introduction............................................................................ 1-1
1.1. Describing Structure ....................................................... 1-2
1.2. Describing Behaviour ...................................................... 1-2
1.3. Discrete Event Time Model............................................... 1-3
1.4. A Quick Example............................................................ 1-3
2. VHDL is Like a Programming Language ................................... 2-1
2.1. Lexical Elements ............................................................ 2-1
2.1.1. Comments .......................................................... 2-1
2.1.2. Identifiers........................................................... 2-1
2.1.3. Numbers ............................................................ 2-1
2.1.4. Characters.......................................................... 2-2
2.1.5. Strings ............................................................... 2-2
2.1.6. Bit Strings........................................................... 2-2
2.2. Data Types and Objects .................................................... 2-2
2.2.1. Integer Types ...................................................... 2-3
2.2.2. Physical Types..................................................... 2-3
2.2.3. Floating Point Types............................................. 2-4
2.2.4. Enumeration Types.............................................. 2-4
2.2.5. Arrays................................................................ 2-5
2.2.6. Records .............................................................. 2-7
2.2.7. Subtypes ............................................................. 2-7
2.2.8. Object Declarations .............................................. 2-8
2.2.9. Attributes ........................................................... 2-8
2.3. Expressions and Operators .............................................. 2-9
2.4. Sequential Statements .................................................... 2-10
2.4.1. Variable Assignment.......................................... 2-10
2.4.2. If Statement ....................................................... 2-11
2.4.3. Case Statement................................................... 2-11
2.4.4. Loop Statements ................................................. 2-12
2.4.5. Null Statement ................................................... 2-13
2.4.6. Assertions ......................................................... 2-13
2.5. Subprograms and Packages ............................................ 2-13
2.5.1. Procedures and Functions ................................... 2-14
2.5.2. Overloading ....................................................... 2-16
2.5.3. Package and Package Body Declarations ............... 2-17
2.5.4. Package Use and Name Visibility ......................... 2-18
i v The VHDL Cookbook
Contents (cont'd)
3. VHDL Describes Structure ........................................................ 3-1
3.1. Entity Declarations .......................................................... 3-1
3.2. Architecture Declarations ................................................ 3-3
3.2.1. Signal Declarations .............................................. 3-3
3.2.2. Blocks ................................................................. 3-4
3.2.3. Component Declarations....................................... 3-5
3.2.4. Component Instantiation ...................................... 3-6
4. VHDL Describes Behaviour ....................................................... 4-1
4.1. Signal Assignment.......................................................... 4-1
4.2. Processes and the Wait Statement ..................................... 4-2
4.3. Concurrent Signal Assignment Statements........................ 4-4
4.3.1. Conditional Signal Assignment ............................. 4-5
4.3.2. Selected Signal Assignment .................................. 4-6
5. Model Organisation .................................................................. 5-1
5.1. Design Units and Libraries............................................... 5-1
5.2. Configurations................................................................ 5-2
5.3. Complete Design Example................................................ 5-5
6. Advanced VHDL ...................................................................... 6-1
6.1. Signal Resolution and Buses............................................. 6-1
6.2. Null Transactions ........................................................... 6-2
6.3. Generate Statements........................................................ 6-2
6.4. Concurrent Assertions and Procedure Calls....................... 6-3
6.5. Entity Statements ............................................................ 6-4
7. Sample Models: The DP32 Processor........................................... 7-1
7.1. Instruction Set Architecture............................................. 7-1
7.2. Bus Architecture............................................................. 7-4
7.3. Types and Entity.............................................................. 7-6
7.4. Behavioural Description................................................... 7-9
7.5. Test Bench.................................................................... 7-18
7.6. Register Transfer Architecture....................................... 7-24
7.6.1. Multiplexor ....................................................... 7-25
7.6.2. Transparent Latch ............................................. 7-25
7.6.3. Buffer ............................................................... 7-26
7.6.4. Sign Extending Buffer......................................... 7-28
7.6.5. Latching Buffer.................................................. 7-28
7.6.6. Program Counter Register .................................. 7-28
7.6.7. Register File ...................................................... 7-29

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